74ABT74PW,118 Nexperia

74ABT74 Dual D-type flip-flop with set and reset positive edge-trigger Rev. 3 12 October 2020 Product data sheet 1. General description The 74ABT74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. This device is fully specified for partial power down applications using I . The I circuitry disables the output, preventing the potentially damaging OFF OFF backflow current through the device when it is powered down. 2. Features and benefits Supply voltage range from 4.5 V to 5.5 V BiCMOS high speed and output drive Direct interface with TTL levels Power-up 3-state I circuitry provides partial Power-down mode operation OFF Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT74D -40 C to +85 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74ABT74PW -40 C to +85 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mmNexperia 74ABT74 Dual D-type flip-flop with set and reset positive edge-trigger 4. Functional diagram 4 4 10 S 5 3 1SD 2SD C1 2 1D 6 SD 1 1Q 5 2 1D R D Q 12 2D 2Q 9 3 1CP CP 10 11 2CP S FF 9 1Q 6 11 Q C1 8 2Q 12 RD 1D 8 13 1RD 2RD R 1 13 mna418 mna419 Fig. 1. Logic symbol Fig. 2. IEC logic symbol nSD nRD Q Q nCP nD aaa-024200 Fig. 3. Logic diagram for one flip-flop 5. Pinning information 5.1. Pinning 74ABT74 74ABT74 1RD 1 14 V CC 2 13 1D 2RD 1RD 1 14 V CC 1CP 3 12 2D 13 1D 2 2RD 3 12 1CP 2D 1SD 4 11 2CP 1SD 4 11 2CP 5 10 1Q 2SD 1Q 5 10 2SD 6 9 1Q 2Q 1Q 6 9 2Q GND 7 8 2Q 7 8 GND 2Q aaa-024201 aaa-024202 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 74ABT74 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 3 12 October 2020 2 / 13