74AHC125PW Nexperia

74AHC125 74AHCT125 Quad buffer/line driver 3-state Rev. 04 11 January 2008 Product data sheet 1. General description The 74AHC125 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specied in compliance with JEDEC standard JESD7-A. The 74AHC125 74AHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. The 74AHC125 74AHCT125 is identical to the 74AHC126 74AHCT126 but has active LOW enable inputs. 2. Features Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accepts voltages higher than V CC For 74AHC125 only: operates with CMOS input levels For 74AHCT125 only: operates with TTL input levels ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Multiple package options Specied from - 40 C to +85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC125D - 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74AHCT125D 74AHC125PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74AHCT125PW 74AHC125BQ - 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad at package no leads 14 terminals 74AHCT125BQ body 2.5 3 0.85 mm74AHC125 74AHCT125 NXP Semiconductors Quad buffer/line driver 3-state 4. Functional diagram 2 1A 1Y 3 2 1 1 1OE 3 1 EN1 5 2A 2Y 6 5 6 2OE 4 4 3A 3Y 9 8 9 8 3OE 10 10 nY nA 12 4A 4Y 11 12 11 13 4OE 13 nOE mna229 mna227 mna228 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer) 5. Pinning information 5.1 Pinning 74AHC125 74AHCT125 terminal 1 index area 74AHC125 74AHCT125 2 13 1A 4OE 1OE 1 14 V 1Y 3 12 4A CC 1A 2 13 4OE 2OE 4 11 4Y 1Y 3 12 4A (1) 2A 5 10 3OE GND 2OE 4 11 4Y 2Y 6 9 3A 2A 5 10 3OE 2Y 6 9 3A 001aah082 GND 7 8 3Y 001aae755 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin conguration SO14 and TSSOP14 Fig 5. Pin conguration DHVQFN14 74AHC AHCT125 4 NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 11 January 2008 2 of 15 7 1 GND 1OE 3Y 8 14 V CC