74AHC273PW,112

74AHC273 74AHCT273 Octal D-type flip-flop with reset positive-edge trigger Rev. 4 23 September 2020 Product data sheet 1. General description The 74AHC273 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC273 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR input. The device is useful for applications where only the true output is required and the clock and master reset are common to all storage elements. 2. Features Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than V CC Ideal buffer for MOS microcontroller or memory Common clock and master reset Input levels: For 74AHC273: CMOS level For 74AHCT273: TTL level ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC273D -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74AHCT273D 74AHC273PW -40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74AHCT273PW 74AHC273BQ -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals 74AHCT273BQ body 2.5 4.5 0.85 mmNexperia 74AHC273 74AHCT273 Octal D-type flip-flop with reset positive-edge trigger 4. Functional diagram 11 CP C1 1 R MR 11 3 2 1D CP D0 Q0 3 2 D0 Q0 4 5 D1 Q1 4 5 D1 Q1 7 6 7 6 D2 Q2 D2 Q2 8 9 8 9 D3 Q3 D3 Q3 13 12 13 12 D4 Q4 D4 Q4 14 15 14 15 D5 Q5 D5 Q5 17 16 D6 Q6 17 16 D6 Q6 18 19 D7 Q7 18 19 MR D7 Q7 1 mna763 mna764 Fig. 1. Logic symbol Fig. 2. IEC logic symbol D0 D1 D2 D3 D Q D Q D Q D Q CP CP CP CP FF1 FF2 FF3 FF4 R R R R D D D D CP MR Q0 Q1 Q2 Q3 D4 D5 D6 D7 D Q D Q D Q D Q CP CP CP CP FF5 FF6 FF7 FF8 R R R R D D D D Q4 Q5 Q6 Q7 001aae056 Fig. 3. Logic diagram 74AHC AHCT273 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 4 23 September 2020 2 / 16