74AHC30BQ

74AHC30 74AHCT30 8-input NAND gate Rev. 4 22 July 2015 Product data sheet 1. General description The 74AHC30 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC30 74AHCT30 provides an 8-input NAND function. 2. Features and benefits Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than V CC Input levels: For 74AHC30: CMOS level For 74AHCT30: TTL level ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74AHC30D 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74AHCT30D 74AHC30PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74AHCT30PW 74AHC30BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package no leads 14 terminals 74AHCT30BQ body 2.5 3 0.85 mm 74AHC30GU12 40 C to +125 C XQFN12 plastic, extremely thin quad flat package no leads SOT1174-1 12 terminals body 1.70 2.00 0.50 mm74AHC30 74AHCT30 NXP Semiconductors 8-input NAND gate 4. Marking Table 2. Marking codes Type number Marking 74AHC30D 74AHC30D 74AHCT30D 74AHCT30D 74AHC30PW AHC30 74AHCT30PW AHCT30 74AHC30BQ AHC30 74AHCT30BQ AHT30 1 74AHC30GU12 A3 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram % & < ( ) * + PQ QD P Pin numbers are shown for SO14, TSSOP14 and Pin numbers are shown for SO14, TSSOP14 and DHVQFN14 packages only DHVQFN14 packages only Fig 1. Logic symbol Fig 2. IEC logic symbol % & < ( PQ ) * + Fig 3. Logic diagram 74AHC AHCT30 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 22 July 2015 2 of 17 D D