74AHCT2G125GD Nexperia

74AHC2G125 74AHCT2G125 Dual buffer/line driver 3-state Rev. 3 6 May 2013 Product data sheet 1. General description The 74AHC2G125 and 74AHCT2G125 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH at nOE causes the output to assume a high-impedance OFF-state. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. 2. Features and benefits Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays Multiple package options ESD protection: HBM JESD22-A114E: exceeds 2000 V MM JESD22-A115-A: exceeds 200 V CDM JESD22-C101C: exceeds 1000 V Specified from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC2G125DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74AHCT2G125DP 74AHC2G125DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74AHCT2G125DC 74AHC2G125GD 40 C to +125 C XSON8 plastic extremely thin small outline package no SOT996-2 leads 8 terminals body 3 2 0.5 mm 74AHCT2G125GD74AHC2G125 74AHCT2G125 NXP Semiconductors Dual buffer/line driver 3-state 4. Marking Table 2. Marking codes Type number Marking 74AHC2G125DP A25 74AHCT2G125DP C25 74AHC2G125DC A25 74AHCT2G125DC C25 74AHC2G125GD A25 74AHCT2G125GD C25 5. Functional diagram 1A 1Y 6 2 2 1 1OE 6 1 1 EN1 5 2A 2Y 3 nA nY 5 3 2 7 2OE 7 EN2 nOE mce185 mce186 mna227 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer) 6. Pinning information 6.1 Pinning 74AHC2G125 74AHCT2G125 1OE 1 8 V CC 74AHC2G125 74AHCT2G125 1A 2 7 2OE 2Y 3 6 1Y 1OE 1 8 V CC 1A 2 7 2OE GND 4 5 2A 2Y 3 6 1Y GND 4 5 2A 001aaj261 001aaj260 Transparent top view Fig 4. Pin configuration SOT505-2 (TSSOP8) and Fig 5. Pin configuration SOT996-2 (XSON8) SOT765-1 (VSSOP8) 74AHC AHCT2G125 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 6 May 2013 2 of 16