74ALVCH162827DGGY Nexperia

74ALVCH162827 20-bit buffer/line driver non-inverting with 30 termination resistors 3-state Rev. 2 19 January 2018 Product data sheet 1 General description The 74ALVCH162827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NAND output enables (nOE1 and nOE2) for maximum control flexibility. The 74ALVCH162827 is designed with 30 series resisters in both the pull-up and pull- down output structures. This design reduces line noise in applications such as memory address drivers, clock drivers and bus receivers/transmitters. To ensure the high impedance state during power up or power down, nOEn should be tied to V through a pullup resistor the minimum value of the resistor is determined by CC the current-sinking/current-sourcing capability of the driver. The 74ALVCH162827 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2 Features and benefits CMOS low power consumption MultiByte flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimum noise and ground bounce CC Direct interface with TTL levels (2.7 V to 3.6 V) Bus hold on data inputs Current drive 12 mA at 3.0 V Integrated 30 termination resistors Complies with JEDEC standards: JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V CDM JESD22-C101E exceeds 1000 V 3 Ordering information Table 1.Ordering information Type number Package Temperature range Name Description Version 74ALVCH162827DGG 40 C to +85 C TSSOP56 plastic thin shrink small outline package SOT364-1 56 leads body width 6.1 mmNexperia 74ALVCH162827 20-bit buffer/line driver non-inverting with 30 termination resistors 3-state 4 Functional diagram 1 & 1OE1 EN1 56 1OE2 28 2OE1 & EN2 29 2OE2 55 2 55 54 52 51 49 48 47 45 44 43 1A0 1 1 1Y0 54 3 1A1 1Y1 52 5 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A2 1Y2 51 6 1A3 1Y3 1 1OE1 49 8 1A4 1Y4 48 9 56 1OE2 1A5 1Y5 47 10 1Y0 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9 1A6 1Y6 45 12 1A7 1Y7 44 13 1A8 1Y8 2 3 5 6 8 9 10 12 13 14 43 14 1A9 1Y9 42 15 2A0 1 2 2Y0 41 16 42 41 40 38 37 36 34 33 31 30 2A1 2Y1 40 17 2A2 2Y2 38 19 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A3 2Y3 37 20 2A4 2Y4 28 2OE1 36 21 2A5 2Y5 29 2OE2 34 23 2A6 2Y6 33 24 2Y0 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 2Y9 2A7 2Y7 31 26 2A8 2Y8 30 27 15 16 17 19 20 21 23 24 26 27 2A9 2Y9 aaa-028075 aaa-028076 Figure 1.Logic symbol Figure 2.IEC logic symbol nA0 nA1 nA2 nA3 nA4 nA5 nA6 nA7 nA8 nA9 nOE1 nOE2 nY0 nY1 nY2 nY3 nY4 nY5 nY6 nY7 nY8 nY9 aaa-028077 Figure 3.Logic diagram V CC data input to internal circuit mna705 Figure 4.Bus hold circuit 74ALVCH162827 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. Product data sheet Rev. 2 19 January 2018 2 / 14