Product Information

74AUP1G02GW

74AUP1G02GW electronic component of Nexperia

Datasheet
IC, 2 I/P NOR GATE, LOW PWR, TSSOP5
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.3491 ea
Line Total: USD 0.35

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
0 - Warehouse 1


Ships to you between Mon. 06 May to Fri. 10 May

MOQ : 1
Multiples : 1

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74AUP1G02GW
Nexperia

1 : USD 0.3491
10 : USD 0.2279
100 : USD 0.16
250 : USD 0.1204
500 : USD 0.1032
3000 : USD 0.0937

Read More Specifications

     
Manufacturer
Product Category
Packaging
Logic Type
Output Current
No Of Inputs
Supply Voltage Min
Supply Voltage Max
Logic Case Style
No Of Pins
Operating Temperature Min
Operating Temperature Max
Msl
Svhc
Operating Temperature Range
Supply Voltage Range
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Additional Infomation About Product

74AUP1G02 Low-power 2-input NOR gate Rev. 7 21 January 2015 Product data sheet 1. General description The 74AUP1G02 provides the single 2-input NOR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC This device is fully specified for partial Power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74AUP1G02 NXP Semiconductors Low-power 2-input NOR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G02GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74AUP1G02GM 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP1G02GF 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT891 6 terminals body 1 1 0.5 mm 74AUP1G02GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP1G02GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 74AUP1G02GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin SOT1226 small outline package no leads 5 terminals body 0.8 0.8 0.35 mm 4. Marking Table 2. Marking 1 Type number Marking code 74AUP1G02GW pB 74AUP1G02GM pB 74AUP1G02GF pB 74AUP1G02GN pB 74AUP1G02GS pB 74AUP1G02GX pB 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram % % < < PQ D PQ D P Q Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 74AUP1G02 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 21 January 2015 2 of 21 D

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