74CBTLV3244PW,118

74CBTLV3244 8-bit bus switch with 4-bit output enables Rev. 4 8 April 2019 Product data sheet 1. General description The 74CBTLV3244 is a dual 4-pole, single-throw bus switch. The device features two output enable inputs (nOE) that each control four switch channels. The switches are disabled when the associated nOE input is HIGH. Schmitt trigger action at control inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power-down applications using I . The I circuitry disables the output, preventing the damaging backflow current OFF OFF through the device when it is powered down. 2. Features and benefits Supply voltage range from 2.3 V to 3.6 V High noise immunity Complies with JEDEC standard: JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V CDM AEC-Q100-011 revision B exceeds 1000 V 5 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A I circuitry provides partial Power-down mode operation OFF Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74CBTLV3244PW -40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74CBTLV3244BQ -40 C to +125 C DHVQFN20 plastic dual-in-line compatible thermal SOT764-1 enhanced very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mmNexperia 74CBTLV3244 8-bit bus switch with 4-bit output enables 4. Functional diagram 1A1 1A2 1A3 1A4 2 4 6 8 1 1OE 18 16 14 12 1B1 1B2 1B3 1B4 2A1 2A2 2A3 2A4 11 13 15 17 19 2OE nAn nBn 9 7 5 3 2B1 2B2 2B3 2B4 nOE 001aan303 001aai099 Fig. 1. Logic symbol Fig. 2. Logic diagram (one switch) 5. Pinning information 5.1. Pinning 74CBTLV3244 terminal 1 index area 1A1 2 19 2OE 2B4 3 18 1B1 4 17 1A2 2A4 2B3 5 16 1B2 1A3 6 15 2A3 74CBTLV3244 2B2 7 14 1B3 1A4 8 (1) 13 2A2 GND 1OE 1 20 V CC 9 12 1A1 2 19 2OE 2B1 1B4 2B4 3 18 1B1 1A2 4 17 2A4 001aan306 2B3 5 16 1B2 Transparent top view 1A3 6 15 2A3 (1) This is not a supply pin. The substrate is 2B2 7 14 1B3 attached to this pad using conductive die attach 1A4 8 13 2A2 material. There is no electrical or mechanical 2B1 9 12 1B4 requirement to solder this pad. However, if it is GND 10 11 2A1 soldered, the solder land should remain floating or 001aan304 be connected to GND. Fig. 3. Pin configuration SOT360-1 (TSSOP20) Fig. 4. Pin configuration SOT764-1 (DHVQFN20) 74CBTLV3244 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 4 8 April 2019 2 / 15 10 1 GND 1OE 2A1 11 20 V CC