74HC4075 74HCT4075 Triple 3-input OR gate Rev. 4 4 February 2019 Product data sheet 1. General description The 74HC4075 74HCT4075 is a triple 3-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Complies with JEDEC standard no. 7A Input levels: For 74HC4075: CMOS level For 74HCT4075: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4075D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT4075D 4. Functional diagram 3 1A 1Y 6 4 1B 3 1 5 1C 4 6 5 1 2A 9 1 2 2B 2Y 1 2 8 9 2C 8 A 11 3A 11 1 10 12 3B 3Y Y B 12 10 13 3C 13 C aaa-024793 aaa-024794 aaa-024795 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate)Nexperia 74HC4075 74HCT4075 Triple 3-input OR gate 5. Pinning information 5.1. Pinning 74HC4075 74HCT4075 2A 1 14 V CC 2 13 2B 3C 1A 3 12 3B 1B 4 11 3A 5 10 1C 3Y 1Y 6 9 2Y 7 8 GND 2C aaa-024796 Fig. 4. Pin configuration SOT108-1 (SO14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A 3, 1, 11 data input 1B, 2B, 3B 4, 2, 12 data input 1C, 2C, 3C 5, 8, 13 data input 1Y, 2Y, 3Y 6, 9, 10 data output GND 7 ground (0 V) V 14 supply voltage CC 6. Functional description Table 3. Function table H = HIGH voltage level L = LOW voltage level X = dont care. Inputs Outputs nA nB nC nY L L L L X X H H X H X H H X X H 74HC HCT4075 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 4 4 February 2019 2 / 11