Product Information

74HC174D,653

74HC174D,653 electronic component of Nexperia

Datasheet
Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.5831 ea
Line Total: USD 0.58

9162 - Global Stock
Ships to you between
Wed. 15 May to Fri. 17 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
9162 - WHS 1


Ships to you between Wed. 15 May to Fri. 17 May

MOQ : 1
Multiples : 1

Stock Image

74HC174D,653
Nexperia

1 : USD 0.5831
10 : USD 0.4796
100 : USD 0.3565
500 : USD 0.2979
1000 : USD 0.2369
2500 : USD 0.192
10000 : USD 0.1886
25000 : USD 0.1852
50000 : USD 0.1852

1159 - WHS 2


Ships to you between Thu. 09 May to Wed. 15 May

MOQ : 1
Multiples : 1

Stock Image

74HC174D,653
Nexperia

1 : USD 0.689
3 : USD 0.65
10 : USD 0.5551
25 : USD 0.4238
60 : USD 0.2717

Read More Specifications

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Family
Logic Type
Polarity
Input Type
Output Type
Propagation Delay Time
High Level Output Current
Low Level Output Current
Supply Voltage - Min
Supply Voltage - Max
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Brand
Number Of Input Lines
Number Of Output Lines
Factory Pack Quantity :
Function
Height
Length
Quiescent Current
Width
Number Of Channels
Cnhts
Hts Code
Mxhts
Operating Supply Voltage
Product Type
Reset Type
Subcategory
Taric
Category
Brand Category
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Additional Infomation About Product

74HC174 74HCT174 Hex D-type flip-flop with reset positive-edge trigger Rev. 6 1 September 2021 Product data sheet 1. General description The 74HC174 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC174: CMOS level For 74HCT174: TTL level Six edge-triggered D-type flip-flops Asynchronous master reset Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Latch-up performance exceeds 100 mA per JESD 78 Class II Level B ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V. Multiple package options Specified from -40 C to +85 C and -40 C to +125 C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC174D -40 C to +125 C SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1 74HCT174D 74HC174PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT174PWNexperia 74HC174 74HCT174 Hex D-type flip-flop with reset positive-edge trigger 4. Functional diagram 9 C1 9 CP 1 R 3 2 D0 Q0 4 5 D1 Q1 3 2 1D 6 7 D2 Q2 4 5 11 10 D3 Q3 6 7 13 12 D4 Q4 11 10 14 15 D5 Q5 13 12 MR 14 15 1 aaa-007149 aaa-007150 Fig. 1. Logic symbol Fig. 2. IEC logic symbol D0 D1 D2 D3 D4 D5 D Q D Q D Q D Q D Q D Q FF1 FF2 FF3 FF4 FF5 FF6 CP MR CP MR CP MR CP MR CP MR CP MR CP MR Q0 Q1 Q2 Q3 Q4 Q5 aaa-007151 Fig. 3. Logic diagram 5. Pinning information 5.1. Pinning 74HC174 74HCT174 MR 1 16 V CC 74HC174 Q0 2 15 Q5 74HCT174 3 14 D0 D5 MR 1 16 V CC D1 4 13 D4 Q0 2 15 Q5 D0 3 14 D5 Q1 5 12 Q4 D1 4 13 D4 D2 6 11 D3 Q1 5 12 Q4 D2 6 11 D3 Q2 7 10 Q3 Q2 7 10 Q3 8 9 GND CP GND 8 9 CP aaa-007152 aaa-007154 Fig. 4. Pin configuration SOT109-1 (SO16) Fig. 5. Pin configuration and SOT403-1 (TSSOP16) 74HC HCT174 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 1 September 2021 2 / 14

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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