74HC238PW,112

74HC238 74HCT238 3-to-8 line decoder/demultiplexer Rev. 7 2 September 2021 Product data sheet 1. General description The 74HC238 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four 238 ICs and one inverter. The 238 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Active HIGH mutually exclusive outputs Input levels: For 74HC238: CMOS level For 74HCT238: TTL level Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Latch-up performance exceeds 100 mA per JESD 78 Class II Level B ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC238D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT238D 74HC238PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT238PW 74HC238BQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals 74HCT238BQ body 2.5 3.5 0.85 mmNexperia 74HC238 74HCT238 3-to-8 line decoder/demultiplexer 4. Functional diagram 15 Y0 14 Y1 15 Y0 13 1 Y2 14 Y1 A0 12 2 Y3 13 Y2 3 TO 8 ENABLE A1 A0 1 11 DECODER EXITING 3 Y4 12 Y3 3 TO 8 ENABLE A2 A1 2 10 DECODER EXITING Y5 11 Y4 A2 3 9 Y6 10 Y5 7 Y7 9 Y6 7 Y7 4 E1 5 4 E2 E1 5 6 E3 E2 6 E3 001aag752 001aag753 Fig. 1. Logic symbol Fig. 2. Functional diagram Y0 E1 Y1 E2 Y2 E3 Y3 Y4 Y5 A0 Y6 A1 Y7 A2 001aag754 Fig. 3. Logic diagram 74HC HCT238 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 7 2 September 2021 2 / 15