74HC373PW,112

74HC373 74HCT373 Octal D-type transparent latch 3-state Rev. 8 6 September 2021 Product data sheet 1. General description The 74HC373 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC373: CMOS level For 74HCT373: TTL level 3-state non-inverting outputs for bus oriented applications Common 3-state output enable input ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC373D -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74HCT373D 74HC373PW -40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74HCT373PW 74HC373BQ -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals 74HCT373BQ body 2.5 4.5 0.85 mmNexperia 74HC373 74HCT373 Octal D-type transparent latch 3-state 4. Functional diagram D0 Q0 3 2 D1 Q1 4 5 D2 Q2 7 6 D3 Q3 8 9 LATCH 3-STATE D4 Q4 1 TO 8 OUTPUTS 13 12 Q5 D5 14 15 D6 Q6 17 16 D7 Q7 18 19 LE 11 OE 1 001aae050 Fig. 1. Functional diagram 1 OE EN 11 C1 LE 11 3 2 1D LE D0 Q0 3 2 D0 Q0 4 5 D1 Q1 4 5 D1 Q1 7 6 7 6 D2 Q2 D2 Q2 8 9 8 9 D3 Q3 D3 Q3 13 12 13 12 D4 Q4 D4 Q4 14 15 14 15 D5 Q5 D5 Q5 17 16 D6 Q6 17 16 D6 Q6 18 19 D7 Q7 18 19 OE D7 Q7 1 001aae048 001aae049 Fig. 2. Logic symbol Fig. 3. IEC logic symbol LE LE LE D Q LE 001aae051 Fig. 4. Logic diagram (one latch) 74HC HCT373 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 6 September 2021 2 / 16