Product Information

74HCT03PW,112

74HCT03PW,112 electronic component of Nexperia

Datasheet
Logic Gates QUAD 2-INPUT NAND

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - WHS 1

MOQ : 2400
Multiples : 1

Stock Image

74HCT03PW,112
Nexperia

2400 : USD 0.4102
2500 : USD 0.3919
3000 : USD 0.39
4000 : USD 0.3881
5000 : USD 0.3862
8000 : USD 0.3842
10000 : USD 0.3823
20000 : USD 0.3803
25000 : USD 0.3783
50000 : USD 0.3763
N/A

Obsolete
0 - WHS 2

MOQ : 2400
Multiples : 2400

Stock Image

74HCT03PW,112
Nexperia

2400 : USD 0.2284
4800 : USD 0.2093
12000 : USD 0.2055
26400 : USD 0.203
50400 : USD 0.1979
100800 : USD 0.1903
N/A

Obsolete
     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Product
Logic Function
Logic Family
Number of Gates
Number of Input Lines
Number of Output Lines
High Level Output Current
Low Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Brand
Number Of Lines In/Out
Factory Pack Quantity :
Function
Height
Length
Output Type
Width
Logic Type
Cnhts
Hts Code
Mxhts
Operating Supply Voltage
Product Type
Subcategory
Taric
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74HC03 74HCT03 Quad 2-input NAND gate open-drain output Rev. 6 10 August 2021 Product data sheet 1. General description The 74HC03 74HCT03 is a quad 2-input NAND gate with open-drain outputs. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Input levels: For 74HC03: CMOS level For 74HCT03: TTL level Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC03D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT03D 74HC03PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74HCT03PWNexperia 74HC03 74HCT03 Quad 2-input NAND gate open-drain output 4. Functional diagram 1 3 & 1 1A 2 1Y 3 2 1B 4 4 2A 6 & 2Y 6 5 5 2B Y 9 9 3A 8 3Y 8 & 10 3B 10 A 12 4A 12 4Y 11 11 & 13 4B 13 B GND mna212 aaa-008083 001aab715 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74HC03 74HCT03 74HC03 74HCT03 1 14 1A V CC 1B 2 13 4B 1A 1 14 V CC 1Y 3 12 4A 1B 2 13 4B 1Y 3 12 4A 4 11 2A 4Y 2A 4 11 4Y 2B 5 10 3B 2B 5 10 3B 2Y 6 9 3A 6 9 2Y 3A GND 7 8 3Y GND 7 8 3Y aaa-008084 aaa-008085 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 74HC HCT03 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 10 August 2021 2 / 11

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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