74HCT139PW-Q100J Nexperia

74HC139-Q100 74HCT139-Q100 Dual 2-to-4 line decoder/demultiplexer Rev. 2 14 January 2021 Product data sheet 1. General description The 74HC139-Q100 74HCT139-Q100 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Input levels: For 74HC139-Q100: CMOS level For 74HCT139-Q100: TTL level Demultiplexing capability 2 independent 2-to-4 decoders Multifunction capability Suitable for memory decoding, data routing or code conversion Complies with JEDEC standard no. 7A Active LOW mutually exclusive outputs ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC139D-Q100 -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74 HCT139D-Q100 74HC139PW-Q100 -40 C to +125 C TSSOP16 plastic thin shrink small outline package SOT403-1 16 leads body width 4.4 mm 74HCT139PW-Q100Nexperia 74HC139-Q100 74HCT139-Q100 Dual 2-to-4 line decoder/demultiplexer 4. Functional diagram 1Y0 4 1A0 1Y1 5 2 DECODER 1A1 1Y2 6 3 1 1Y3 7 1E 1E 1Y0 4 1 2 1A0 1Y1 5 2Y0 12 1Y2 6 3 1A1 2A0 2Y1 1Y3 7 11 14 DECODER 2Y0 12 2A1 2Y2 14 2A0 10 13 2Y1 11 2Y3 9 2Y2 10 13 2A1 2Y3 9 2E 2E 15 15 aaa-012173 aaa-012174 Fig. 1. Logic symbol Fig. 2. Functional diagram DX X/Y 2 4 2 4 0 0 1 0 0 G 3 5 3 5 3 1 1 2 1 6 6 2 2 1 7 1 7 3 EN 3 DX X/Y 14 12 14 12 0 0 1 0 0 G 13 11 13 11 3 1 1 2 1 10 10 2 2 15 9 15 9 3 EN 3 aaa-012176 aaa-012177 Fig. 3. IEC Logic symbol Y0 A0 Y1 A1 Y2 E Y3 aaa-012175 Fig. 4. Logic diagram (one decoder/demultiplexer) 74HC HCT139 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 2 14 January 2021 2 / 13