74LV245D Nexperia

74LV245 Octal bus transceiver 3-state Rev. 03 15 April 2009 Product data sheet 1. General description The 74LV245 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC245 and 74HCT245. The 74LV245 is an octal transceiver with non-inverting 3-state bus compatible outputs in both send and receive directions. A send/receive (DIR) input controls direction, and an output enable (OE) input makes easy cascading possible. Pin OE controls the outputs so that the buses are effectively isolated. 2. Features n Wide operating voltage: 1.0 V to 5.5 V n Optimized for low voltage applications: 1.0 V to 3.6 V n Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC n Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb n Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T =25 C amb n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Multiple package options n Specied from - 40 Cto+85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV245N - 40 C to +125 C DIP20 plastic dual in-line package 20 leads (300 mil) SOT146-1 74LV245D - 40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LV245DB - 40 C to +125 C SSOP20 plastic shrink small outline package 20 leads SOT339-1 body width 5.3 mm 74LV245PW - 40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm74LV245 NXP Semiconductors Octal bus transceiver 3-state 4. Functional diagram DIR 1 OE 19 A0 2 B0 18 A1 3 B1 17 A2 4 19 G3 B2 1 16 3EN1 3EN2 A3 5 B3 15 1 A4 18 2 6 2 B4 14 3 17 A5 7 4 16 B5 13 5 15 A6 8 6 14 B6 12 7 13 A7 9 8 12 B7 11 9 11 mna174 mna175 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LV245 3 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 15 April 2009 2 of 15