74LV4060D,118 Nexperia

74LV4060 14-stage binary ripple counter with oscillator Rev. 5 24 March 2021 Product data sheet 1. General description The 74LV4060 is a 14-stage ripple-carry counter/divider and oscillator with three oscillator terminals (RS, R and C ), ten buffered parallel outputs (Q to Q and Q to Q ) and an TC TC 3 9 11 13 overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case, keep the oscillator pins (R and C ) floating. The counter advances on the TC TC HIGH-to-LOW transition of RS. A HIGH level on MR clears all counter stages and forces all outputs LOW, independent of the other input conditions. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess V . CC 2. Features and benefits Wide supply voltage range from 1.0 V to 5.5 V Optimized for low voltage applications from 1.0 V to 3.6 V CMOS low power dissipation Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical V (output ground bounce) < 0.8 V at V = 3.3 V T = 25 C OLP CC amb Typical V (output V undershoot) > 2 V at V = 3.3 V T = 25 C OHV OH CC amb All active components on-chip RC or crystal oscillator configuration Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115A exceeds 200 V 3. Applications Control counters Timers Frequency dividers Time-delay circuits 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV4060D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LV4060PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mmNexperia 74LV4060 14-stage binary ripple counter with oscillator 5. Functional diagram 10 9 CTR14 CTR14 RTC CTC 3 7 3 7 G RS Q3 7 9 CTC 5 5 11 Q4 5 10 RTC 4 4 + MR 12 Q5 4 11 RS 6 11 AND 6 + Q6 6 12 MR 14 12 14 CT CT Q7 14 13 13 Q8 13 CT = 0 9 15 CT = 0 9 15 Q9 15 11 1 11 1 Q11 1 2 2 Q12 2 13 3 13 3 Q13 3 (a) (b) 001aai467 001aai468 Fig. 1. Logic symbol Fig. 2. IEC logic symbol CTC FF FF FF FF FF RTC 1 4 10 12 14 RS CP CP CP CP CP Q Q Q Q Q MR MR MR MR MR MR Q3 Q9 Q11 Q13 001aai114 Fig. 3. Logic diagram 10 9 RTC CTC RS 11 CP 14-STAGE BINARY COUNTER MR MR 12 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q11 Q12 Q13 7 5 4 6 14 13 15 1 2 3 001aai113 Fig. 4. Functional diagram 74LV4060 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 24 March 2021 2 / 17