74LVC1G126GW-Q100H Nexperia

74LVC1G126-Q100 Bus buffer/line driver 3-state Rev. 4 3 May 2021 Product data sheet 1. General description The 74LVC1G126-Q100 is a single buffer/line driver with 3-state output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . OFF The I circuitry disables the output, preventing the potentially damaging backflow current through OFF the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation I circuitry provides partial Power-down mode operation OFF 24 mA output drive (V = 3.0 V) CC Latch-up performance exceeds 250 mA Direct interface with TTL levels Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G126GW-Q100 -40 C to +125 C TSSOP5 plastic thin shrink small outline package SOT353-1 5 leads body width 1.25 mm 74LVC1G126GV-Q100 -40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753Nexperia 74LVC1G126-Q100 Bus buffer/line driver 3-state 4. Marking Table 2. Marking codes Type number Marking 1 74LVC1G126GW-Q100 VN 74LVC1G126GV-Q100 V26 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 2 A Y 4 A Y 2 4 OE 1 1 OE OE mna125 mna126 mna127 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74LVC1G126 OE 1 5 V CC A 2 GND 3 4 Y 001aaf196 Fig. 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A) 6.2. Pin description Table 3. Pin description Symbol Pin Description OE 1 output enable input A 2 data input GND 3 ground (0 V) Y 4 data output V 5 supply voltage CC 74LVC1G126 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 3 May 2021 2 / 13