74LVC1GU04GX,125

74LVC1GU04 Unbuffered inverter Rev. 12 9 April 2013 Product data sheet 1. General description The 74LVC1GU04 is a single unbuffered inverter. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V High noise immunity ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (V =3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Input accepts voltages up to 5 V Multiple package options Specified from 40 Cto+85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1GU04GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package SOT353-1 5 leads body width 1.25 mm 74LVC1GU04GV 40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 74LVC1GU04GM 40 C to +125 C XSON6 plastic extremely thin small outline package SOT886 no leads 6 terminals body 1 1.45 0.5 mm 74LVC1GU04GF 40 C to +125 C XSON6 plastic extremely thin small outline package SOT891 no leads 6 terminals body 1 1 0.5 mm 74LVC1GU04GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74LVC1GU04GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 74LVC1GU04GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely SOT1226 thin small outline package no leads 5 terminals body 0.8 0.8 0.35 mm74LVC1GU04 NXP Semiconductors Unbuffered inverter 4. Marking Table 2. Marking codes 1 Type number Marking 74LVC1GU04GW VD 74LVC1GU04GV VU4 74LVC1GU04GM VD 74LVC1GU04GF VD 74LVC1GU04GN VD 74LVC1GU04GS VD 74LVC1GU04GX VD 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram V V CC CC 100 Y A 2AY 4 1 2 4 mna108 mna109 mna636 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74LVC1GU04 74LVC1GU04 n.c. 1 6 V CC n.c. 1 5 V CC A 2 5 n.c. A 2 GND 3 4 Y GND 3 4 Y 001aab667 Transparent top view 001aab666 Fig 4. Pin configuration SOT353-1 and SOT753 Fig 5. Pin configuration SOT886 74LVC1GU04 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 12 9 April 2013 2 of 20