74LVC573ADB,112

74LVC573A Octal D-type transparent latch with 5 V tolerant inputs/outputs 3-state Rev. 8 27 August 2021 Product data sheet 1. General description The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.2 to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power consumption Direct interface with TTL levels I circuitry provides partial Power-down mode operation OFF High-impedance when V = 0 V CC Flow-through pinout architecture Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 CNexperia 74LVC573A Octal D-type transparent latch with 5 V tolerant inputs/outputs 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC573AD -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVC573APW -40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74LVC573ABQ -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mm 4. Functional diagram 11 C1 1 EN1 1 2 19 1D OE 2 19 D0 Q0 3 18 3 18 D1 Q1 4 17 4 17 D2 Q2 5 16 5 16 D3 Q3 6 15 6 15 D4 Q4 7 14 7 14 D5 Q5 8 13 D6 Q6 8 13 9 12 D7 Q7 9 12 LE mna807 11 mna808 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 2 D0 Q0 19 3 D1 Q1 18 4 D2 17 Q2 5 D3 Q3 16 LATCH 3-STATE 6 D4 Q4 15 1 to 8 OUTPUTS 7 D5 Q5 14 8 13 D6 Q6 9 D7 Q7 12 11 LE 1 OE mna809 Fig. 3. Functional diagram 74LVC573A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 27 August 2021 2 / 16