74LVT16373ADGG,112

74LVT16373A 3.3 V 16-bit transparent D-type latch 3-state Rev. 4 3 August 2021 Product data sheet 1. General description The 74LVT16373A is a 16-bit D-type transparent latch with 3-state outputs. The device can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The device features two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs 2. Features and benefits 16-bit transparent latch 3-state buffers Wide supply voltage range from 2.7 to 3.6 V BiCMOS high speed and output drive Output capability: +64 mA/32 mA Direct interface with TTL levels Overvoltage tolerant inputs to 5.5 V Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion/extraction permitted Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 500 mA per JESD 78 Class II Level B Complies with JEDEC standard JESD8C (2.7 V to 3.6 V) ESD protection: HBM: JESD22-A114F exceeds 2000 V MM: JESD22-A115-A exceeds 200 V Specified from -40 C to 85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT16373ADGG -40 C to +85 C TSSOP48 plastic thin shrink small outline package 48 leads SOT362-1 body width 6.1 mmNexperia 74LVT16373A 3.3 V 16-bit transparent D-type latch 3-state 4. Functional diagram 1 1EN 1OE 48 1LE C3 1 24 24 2OE 2EN 25 C4 2LE 1OE 2OE 47 1D0 1Q0 2 2 47 1D0 1 1Q0 3D 46 1D1 1Q1 3 46 3 1D1 1Q1 44 1D2 1Q2 5 44 5 1D2 1Q2 43 1D3 1Q3 6 43 6 1D3 1Q3 41 1D4 1Q4 8 8 41 1D4 1Q4 40 1D5 1Q5 9 9 40 38 1D6 1Q6 11 1D5 1Q5 38 11 37 1D7 1Q7 12 1D6 1Q6 37 12 36 2D0 2Q0 13 1D7 1Q7 36 13 35 2D1 2Q1 14 2D0 4D 2 2Q0 33 2D2 2Q2 16 35 14 2D1 2Q1 32 2D3 2Q3 17 16 33 2D2 2Q2 30 2D4 2Q4 19 17 32 2D3 2Q3 29 2D5 2Q5 20 30 19 2D4 2Q4 27 2D6 2Q6 22 29 20 2D5 2Q5 26 2D7 2Q7 23 27 22 2D6 2Q6 1LE 2LE 26 23 2D7 2Q7 48 25 001aam007 mgu770 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 1D0 D Q 1Q0 2D0 D Q 2Q0 LATCH LATCH 1 9 LE LE LE LE 1LE 2LE 1OE 2OE to 7 other channels to 7 other channels mgu769 Fig. 3. Logic diagram 74LVT16373A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 3 August 2021 2 / 13