Product Information

74LVC574APW,112

74LVC574APW,112 electronic component of Nexperia

Datasheet
Flip Flops 3.3V OCTAL D FF POS
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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Obsolete

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Availability Price Quantity
0 - WHS 1

MOQ : 1
Multiples : 1
1 : USD 0.4539
10 : USD 0.3994
75 : USD 0.3349
525 : USD 0.2847
1050 : USD 0.2103
2550 : USD 0.2082
5025 : USD 0.2076
N/A

Obsolete
0 - WHS 2

MOQ : 1
Multiples : 1
1 : USD 0.4495
75 : USD 0.3619
150 : USD 0.2895
525 : USD 0.2274
1050 : USD 0.1757
N/A

Obsolete
0 - WHS 3

MOQ : 150
Multiples : 150
150 : USD 0.1514
375 : USD 0.1406
1875 : USD 0.1352
3750 : USD 0.1298
11250 : USD 0.1298
N/A

Obsolete
0 - WHS 4

MOQ : 1
Multiples : 1
1 : USD 0.8518
10 : USD 0.7276
75 : USD 0.4266
525 : USD 0.3423
1050 : USD 0.2763
2550 : USD 0.2456
5025 : USD 0.2315
N/A

Obsolete
0 - WHS 5

MOQ : 525
Multiples : 75
525 : USD 0.2295
1000 : USD 0.1773
N/A

Obsolete

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RoHS - XON
Icon ROHS
Number of Circuits
Logic Family
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Input Type
Propagation Delay Time
High Level Output Current
Supply Voltage - Min
Supply Voltage - Max
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Additional Infomation About Product

74LVC574A Octal D-type flip-flop with 5 V tolerant inputs/outputs positive edge-trigger 3-state Rev. 6 30 August 2021 Product data sheet 1. General description The 74LVC574A is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using I . The I circuitry OFF OFF disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.2 to 3.6 V CMOS low power consumption Direct interface with TTL levels Overvoltage tolerant inputs to 5.5 V High-impedance when V = 0 V CC 8-bit positive edge-triggered register Independent register and 3-state buffer operation Flow-through pin-out architecture I circuitry provides partial Power-down mode operation OFF Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 CNexperia 74LVC574A Octal D-type flip-flop with 5 V tolerant inputs/outputs positive edge-trigger 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC574AD -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVC574APW -40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74LVC574ABQ -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mm 4. Functional diagram 11 C1 1 EN D0 2 Q0 19 11 3 D1 Q1 18 2 19 CP 1D 4 D2 Q2 17 2 19 D0 Q0 D3 FF1 Q3 3 18 5 16 3-STATE 3 18 to D1 Q1 6 D4 OUTPUTS Q4 15 4 17 FF8 4 17 D2 Q2 7 D5 Q5 14 5 16 5 16 D3 Q3 8 Q6 13 D6 6 15 6 15 D4 Q4 D7 9 Q7 12 7 14 D5 7 14 Q5 8 13 D6 Q6 11 CP 8 13 9 12 D7 Q7 1 OE 9 12 OE 1 mna798 mna446 mna800 Fig. 1. Logic diagram Fig. 2. IEC logic symbol Fig. 3. Functional diagram D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q CP CP CP CP CP CP CP CP FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q 7 mna801 Fig. 4. Logic diagram 74LVC574A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 30 August 2021 2 / 15

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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