HEF4027BT,652 Nexperia

HEF4027B Dual JK flip-flop Rev. 11 7 December 2021 Product data sheet 1. General description The HEF4027B is a dual positive-edge triggered JK flip-flop featuring independent set direct (nSD), clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ). Data is accepted when nCP is LOW, and transferred to the output on the positive-going edge of the clock. The asynchronous clear-direct (nCD) and set-direct (nSD) are independent and override the nJ, nK, and nCP inputs. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . DD 2. Features and benefits Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V Specified from -40 C to +85 C 3. Applications Registers Counters Control circuits 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4027BT -40 C to +85 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mmNexperia HEF4027B Dual JK flip-flop 5. Functional diagram FF 1 9 1SD 10 1J 1Q 15 13 1CP 1Q 14 1K 11 1CD 12 FF 2 7 2SD 6 2J 2Q 1 3 2CP 2Q 2 2K 5 2CD 4 001aae593 Fig. 1. Functional diagram CP C Q C C C C C J C C Q K C C CD SD 001aae595 Fig. 2. Logic diagram of one flip-flop HEF4027B All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 11 7 December 2021 2 / 11