MPC5534MVM80

Document Number: MPC5534 Freescale Semiconductor Rev. 6, Apr 2012 Data Sheet: Technical Data MPC5534 Microcontroller Data Sheet by: Automotive and Industrial Solutions Gruop Contents This document provides electrical specifications, pin 1 Overview . 1 assignments, and package diagrams for the MPC5534 2 Ordering Information 3 microcontroller device. For functional characteristics, 3 Electrical Characteristics . 4 refer to the MPC5534 Microcontroller Reference 3.1 Maximum Ratings 4 Manual. 3.2 Thermal Characteristics . 5 3.3 Package 8 3.4 EMI Characteristics . 8 3.5 ESD Characteristics 9 1 Overview 3.6 VRC and POR Electrical Specifications . 9 3.7 Power-Up/Down Sequencing . 10 The MPC5534 microcontroller (MCU) is a member of 3.8 DC Electrical Specifications . 14 the MPC5500 family of microcontrollers built on the 3.9 Oscillator and FMPLL Electrical Characteristics 20 3.10 eQADC Electrical Characteristics . 22 Power Architecture embedded technology. This family 3.11 H7Fb Flash Memory Electrical Characteristics . 23 of parts has many new features coupled with high 3.12 AC Specifications . 24 performance CMOS technology to provide substantial 3.13 AC Timing . 26 4 Mechanicals 46 reduction of cost per feature and significant performance 4.1 MPC5534 208 MAP BGA Pinout 46 improvement over the MPC500 family. 4.2 MPC5534 324 PBGA Pinouts 47 4.3 MPC5534 208-Pin Package Dimensions 48 The host processor core of this device complies with the 4.4 MPC5534 324-Pin Package Dimensions 50 Power Architecture embedded category that is 100% 5 Revision History for the MPC5534 Data Sheet . 52 5.1 Changes Between Revisions 5.0 and 6.0 . 52 user-mode compatible (including floating point library) 5.3 Changes Between Revisions 3.0 and 4.0 . 53 with the original PowerPC instruction set. The embedded architecture enhancements improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original PowerPC instruction set. Freescale Semiconductor, Inc., 2008-2012. All rights reserved.Overview The MPC5500 family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The host processor core of the MPC5534 also includes an instruction set enhancement allowing variable length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this enhancement, it is possible to significantly reduce the code size footprint. The MPC5534 has a single-level memory hierarchy consisting of 64-kilobytes (KB) on-chip SRAM and one megabyte (MB) of internal flash memory. Both the SRAM and the flash memory can hold instructions and data. The external bus interface (EBI) supports most standard memories used with the MPC5xx family. The MPC5534 does not support arbitration with other masters on the external bus. The MPC5534 must be the only master on the external bus, or act as a slave-only device. The complex input/output timer functions of the MPC5534 are performed by an enhanced time processor unit (eTPU) engine. The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is programmed using a high-level programming language. The less complex timer functions of the MPC5534 are performed by the enhanced modular input/output system (eMIOS). The eMIOS 24 hardware channels are capable of single-action, double-action, pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including controller area networks (FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications interfaces (eSCIs). The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC) with a 5 V conversion range. The 324 package has 40-channels the 208 package has 34 channels. The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset control are also determined by the SIU. The internal multiplexer sub-block (IMUX) provides multiplexing of eQADC trigger sources and external interrupt signal multiplexing. MPC5534 Microcontroller Data Sheet, Rev. 6 2 Freescale Semiconductor