PSMN1R0-25YLD N-channel 25 V, 1.0 m, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology 23 June 2020 Product data sheet 1. General description Logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package. NextPowerS3 portfolio utilising Nexperias unique SchottkyPlus technology delivers high efficiency, low spiking performance usually associated with MOSFETS with an integrated Schottky or Schottky-like diode but without problematic high leakage current. NextPowerS3 is particularly suited to high efficiency applications at high switching frequencies. 2. Features and benefits Avalanche rated, 100% tested at I = 190 A AS Ultra low Q , Q and Q for high system efficiency, especially at higher switching G GD OSS frequencies Superfast switching with soft-recovery Low spiking and ringing for low EMI designs Unique SchottkyPlus technology Schottky-like performance with < 1 A leakage at 25 C Optimised for 4.5 V gate drive Low parasitic inductance and resistance High reliability clip bonded and solder die attach Power SO8 package no glue, no wire bonds, qualified to 175 C Wave solderable exposed leads for optimal visual solder inspection 3. Applications On-board DC:DC solutions for server and telecommunications Secondary-side synchronous rectification in telecommunication applications Voltage regulator modules (VRM) Point-of-Load (POL) modules Power delivery for V-core, ASIC, DDR, GPU, VGA and system components Brushed and brushless motor control Power OR-ing 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit V drain-source voltage 25 C T 175 C - - 25 V DS j I drain current V = 10 V T = 25 C Fig. 2 1 - - 240 A D GS mb P total power dissipation T = 25 C Fig. 1 - - 160 W tot mb T junction temperature -55 - 175 C j Static characteristics R drain-source on-state V = 10 V I = 25 A T = 25 C - 0.89 1 m DSon GS D j resistance Fig. 10Nexperia PSMN1R0-25YLD N-channel 25 V, 1.0 m, 240 A logic level MOSFET in LFPAK56 using NextPowerS3 Technology Symbol Parameter Conditions Min Typ Max Unit V = 4.5 V I = 25 A T = 25 C - 1.19 1.43 m GS D j Fig. 10 Dynamic characteristics Q gate-drain charge I = 25 A V = 12 V V = 4.5 V - 8 - nC GD D DS GS Fig. 12 Fig. 13 Q total gate charge I = 25 A V = 12 V V = 10 V - 71.8 - nC G(tot) D DS GS Fig. 12 Fig. 13 Avalanche ruggedness E non-repetitive drain- I = 25 A V 25 V R = 50 2 3 - - 1762 mJ DS(AL)S D sup GS source avalanche V = 10 V T = 25 C unclamped GS j(init) energy t = 4.34 ms p Source-drain diode Q recovered charge I = 25 A dI /dt = -100 A/s V = 0 V 4 - 36.7 - nC r S S GS V = 12 V Fig. 16 DS 1 240A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB thermal design and operating temperature. 2 Single-pulse avalanche rating limited by maximum junction temperature of 175 C. 3 Refer to application note AN10273 for further information. 4 includes capacitive recovery 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 S source mb D 2 S source G 3 S source 4 G gate mbb076 S mb D mounting base connected 1 2 3 4 to drain LFPAK56 Power- SO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number Package Name Description Version PSMN1R0-25YLD LFPAK56 plastic, single-ended surface-mounted package 4 terminals SOT669 Power-SO8 7. Marking Table 4. Marking codes Type number Marking code PSMN1R0-25YLD 1D025L PSMN1R0-25YLD All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet 23 June 2020 2 / 14