NTE937M Integrated Circuit JFET Input Operational Amplifier Description: The NTE937M is a monolithic JFET input operational amplifier in an 8Lead DIP type package incor- porating wellmatched, high voltage JFETs on the same chip with standard bipolar transistors. This amplifier features low input bias and offset currents, low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or commonmode rejection. It is also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner. Advantages: Replaces Expensive Hybrid and Module FET OP Amps Rugged JFETs Allow BlowOut Free Handling Compared with MOSFET Input Device Excellent for Low Noise Applications using either High or Low Source Impedance Very Low 1/f Corner Offset Adjust does not Degrade Drift or CommonMode Rejection as in Most Monolithic Amplifiers New Output Stage Allows use of Large Capacitive Loads (10,000pF) without Stability Problems Internal Compensation and Large Differential Input Voltage Capability Applications: Precision High Speed Integrators Fast D/A and A/D Converters High Impedance Buffers Wideband, Low Noise, Low Drift Amplifiers Logarithmic Amplifiers Photocell Amplifiers Sample and Hold Circuits Absolute Maximum Ratings: Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Maximum Power Dissipation (at +25C, Note 1), P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW d Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Input Voltage Range (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V Output ShortCircuit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Maximum Operating Junction Temperature (Note 1), T max . . . . . . . . . . . . . . . . . . . . . . . . . . +100C J Storage Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to +150C stg Lead Temperature (During Soldering, 10sec), T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C L Thermal Resistance, JunctiontoAmbient (Note 1), R . . . . . . . . . . . . . . . . . . . . . . . . . +155C/W thJC Note 1. The maximum power dissipation for this device must be derated at elevated temperatures and is dictated by T max, R , and the ambient temperature, T . The maximum available J thJC A power dissipation at any temperature is P = (T max T )/R or the +25C P max, which- d J A thJC d ever is less. Note 2. Unless otherwise specified, the absolute maximum negative input voltage is equal to the negative power supply voltage.DC Electrical Characteristics: (T = +25C, V = 15V unless otherwise specified) A S Parameter Symbol Test Conditions Min Typ Max Unit Supply Current I 5 10 mA CC DC Electrical Characteristics: (V = 15V, 0 T +70C, T = +70C unles otherwise S A HIGH specified) Parameter Symbol Test Conditions Min Typ Max Unit Input Offset Voltage V R = 50 , T = +25C 3 10 mV OS S A Over Temperature 13 mV Average TC of Input Offset Voltage V / T R = 50 5 V/C OS S Change in Average TC with V TC/ V R = 50 , Note 3 0.5 V/C OS OS S Adjust Input Offset Current I T = +25C, Note 4 3 50 pA OS J T T 2 nA J HIGH Input Bias Current I T = +25C, Note 4 30 200 pA B J T T 8 nA J HIGH 12 Input Resistance R T = +25C 10 IN J Large Signal Voltage Gain A T = +25C, V = 10V, 25 200 V/mV VOL A O R = 2k L Over Temperature 15 V/mV Output Voltage Swing V R = 10k 12 13 V O L R = 2k 10 12 V L Input CommonMode Voltage Range V 10 +15.1 V CM 12 CommonMode Rejection Ratio CMRR 80 100 dB Supply Voltage Rejection Ratio PSRR Note 5 80 100 dB Note 3. The temperature coeficient of the adjust input offset voltage changes only a small amount (0.5 V/C typically) for each mV of adjustment from its original unadjusted value. Common mode rejection and open loop voltage gain are also unaffected by offset adjustment. Note 4. The input bias currents are junction leakage currents which approximately double for every 10C increase in the junction temperature, T . Due to limited production test time, the input J bias currents measured are correlated to junction temperature. In normal operation the junc- tion temperature rises above the ambient temperature as a result of internal power dissipa- tion, P . T = T + R P where R is the thermal resistance from junction to ambient. d J A thJC d thJC Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 5. Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.