74AHC259PW,118

74AHC259 74AHCT259 8-bit addressable latch Rev. 02 15 May 2008 Product data sheet 1. General description The 74AHC259 74AHCT259 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specied in compliance with JEDEC standard No. 7-A. The 74AHC259 74AHCT259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single-line data in eight addressable latches and providing a 3-to-8 decoder and multiplexer function with active HIGH outputs (Q0 to Q7). It also incorporates an active LOW common reset (MR) for resetting all latches as well as an active LOW enable input (LE). The 74AHC259 74AHCT259 has four modes of operation: In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the data input (D) with all other outputs in the LOW state. In the reset mode, all outputs are LOW and unaffected by the address inputs (A0 to A2) and data input (D). When operating the 74AHC259 74AHCT259 as an address latch, changing more than one bit of the address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. 2. Features n Balanced propagation delays n All inputs have Schmitt-trigger actions n Combines demultiplexer and 8-bit latch n Serial-to-parallel capability n Output from each storage bit available n Random (addressable) data entry n Easily expandable n Common reset input n Useful as a 3-to-8 active HIGH decoder n Inputs accept voltages higher than V CC74AHC259 74AHCT259 NXP Semiconductors 8-bit addressable latch n Input levels: u For 74AHC259: CMOS level u For 74AHCT259: TTL level n ESD protection: u HBM EIA/JESD22-A114E exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V u CDM EIA/JESD22-C101C exceeds 1000 V n Multiple package options n Specied from - 40 C to +85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC259 74AHC259D - 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74AHC259PW - 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74AHCT259 74AHCT259D - 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74AHCT259PW - 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 4. Functional diagram 13 Z9 15 G8 14 G10 9,10D DX 4 14 C10 1 0 8R 1 LE 0 5 2 4 0 Q0 G 1 7 3 13 5 6 2 D Q1 2 6 7 Q2 7 3 Q3 9 1 9 A0 Q4 4 2 10 10 A1 Q5 5 3 11 A2 Q6 11 12 6 Q7 12 MR 7 15 mna573 mna572 Fig 1. Logic symbol Fig 2. IEC logic symbol 74AHC AHCT259 2 NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 15 May 2008 2 of 17