74HC08D NXP

74HC08 74HCT08 Quad 2-input AND gate Rev. 5 30 November 2015 Product data sheet 1. General description The 74HC08 74HCT08 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Complies with JEDEC standard JESD7A Input levels: For 74HC08: CMOS level For 74HCT08: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC08D 40 C to +125 C SO14 plastic small outline package 14 leads body width SOT108-1 3.9 mm 74HCT08D 74HC08DB 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads body SOT337-1 width 5.3 mm 74HCT08DB 74HC08PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74HCT08PW 74HC08BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package no leads 14 terminals 74HCT08BQ body 2.5 3 0.85 mm&& 74HC08 74HCT08 NXP Semiconductors Quad 2-input AND gate 4. Functional diagram < < < < < % Q P QD P D PQ Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning + & + &7 + 7& WHUP LQDO 9 9 LQGH DUHD % % % < < < % % % < < DDD DDD UDQVSDUHQW WRS H Y Z 7 L (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 74HC HCT08 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 5 30 November 2015 2 of 15 *1 < < *1 % *1 < % && +& D % % % %