Product Information

74HC03D

74HC03D electronic component of Nexperia

Datasheet
Logic Gates QUAD 2-INPUT NAND GATE OC

Manufacturer: Nexperia
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Price (USD)

5: USD 0.4568 ea
Line Total: USD 2.28

0 - Global Stock
MOQ: 5  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 5
Multiples : 1

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74HC03D
Nexperia

5 : USD 0.4568
50 : USD 0.3489
100 : USD 0.258
500 : USD 0.2219
1000 : USD 0.1851

     
Manufacturer
Product Category
Package / Case
Brand
Logic Family / Base Number
Logic Type
Output Current
No. Of Inputs
Supply Voltage Min
Supply Voltage Max
Logic Case Style
No. Of Pins
Logic Ic Family
Logic Ic Base Number
Operating Temperature Min
Operating Temperature Max
Rohs Phthalates Compliant
Msl
Svhc
Base Number
Ic Generic Number
Logic Function Number
Logic Ic Function
No. Of Gates
Operating Temperature Range
Output Current Max
Supply Voltage
Supply Voltage Range
Termination Type
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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT03 Quad 2-input NAND gate December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Quad 2-input NAND gate 74HC/HCT03 FEATURES The 74HC/HCT03 provide the 2-input NAND function. The 74HC/HCT03 have open-drain N-transistor outputs, Level shift capability which are not clamped by a diode connected to V . In CC Output capability: standard (open drain) the OFF-state, i.e. when one input is LOW, the output I category: SSI CC may be pulled to any voltage between GND and V . Omax This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and GENERAL DESCRIPTION OR-tied output applications, these devices must have a The 74HC/HCT03 are high-speed Si-gate CMOS devices pull-up resistor to establish a logic HIGH level. and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay C = 15 pF R =1 k V = 5 V 8 10 ns PZL PLZ L L CC C input capacitance 3.5 3.5 pF I C power dissipation capacitance per gate notes 1, 2 and 3 4.0 4.0 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 2 P =C V f + (C V f ) + (V /R ) duty factor LOW, where: D PD CC i L CC o O L f = input frequency in MHz i f = output frequency in MHz o V = output voltage in V O C = output load capacitance in pF L V = supply voltage in V CC R = pull-up resistor in M L 2 (C V f ) = sum of outputs L CC o 2 (V /R ) = sum of outputs O L 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC 3. The given value of C is obtained with: PD C = 0 pF and R = L L ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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