74HC273PW-Q100J NXP

74HC273-Q100 74HCT273-Q100 Octal D-type flip-flop with reset positive-edge trigger Rev. 1 19 June 2013 Product data sheet 1. General description The 74HC273-Q100 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes which enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Input levels: For 74HC273-Q100: CMOS level For 74HCT273-Q100: TTL level Common clock and master reset Eight positive edge-triggered D-type flip-flops Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V. Multiple package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC273D-Q100 40 C to +125 C SO20 plastic small outline package 20 leads body width SOT163-1 7.5 mm 74HCT273D-Q100 74HC273PW-Q100 40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74HCT273PW-Q100 74HC273BQ-Q100 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals 74HCT273BQ-Q100 body 2.5 4.5 0.85 mm74HC273-Q100 74HCT273-Q100 Nexperia Octal D-type flip-flop with reset positive-edge trigger 4. Functional diagram 11 CP C1 1 R MR 11 3 2 D0 1D Q0 D0 Q0 CP 3 2 3 2 D1 Q1 D0 Q0 4 5 4 5 D1 Q1 4 5 D2 Q2 D1 Q1 7 6 7 6 7 6 D3 Q3 D2 Q2 FF1 D2 Q2 8 9 D4 TO Q4 8 9 8 9 13 12 D3 Q3 D3 Q3 FF8 D5 Q5 13 12 13 12 14 15 D4 Q4 D4 Q4 D6 Q6 17 16 14 15 14 15 D5 Q5 D7 Q7 D5 Q5 18 19 17 16 D6 Q6 17 16 MR D6 Q6 18 19 1 D7 Q7 CP 18 19 MR 11 D7 Q7 001aae055 1 mna763 mna764 Fig 1. Functional diagram Fig 2. Logic symbol Fig 3. IEC logic symbol 74HC HCT273 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 1 19 June 2013 2 of 19