74HC193 74HCT193 Presettable synchronous 4-bit binary up/down counter Rev. 7 8 September 2021 Product data sheet 1. General description The 74HC193 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR) it may also be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Input levels: For 74HC193: CMOS level For 74HCT193: TTL level Synchronous reversible 4-bit binary counting Asynchronous parallel load Asynchronous reset Expandable without external logic Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V. Specified from -40 C to +85 C and -40 C to +125 C.Nexperia 74HC193 74HCT193 Presettable synchronous 4-bit binary up/down counter 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74HC193D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT193D 74HC193PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT193PW 4. Functional diagram 15 1 10 9 D0 D1 D2 D3 PL TCU 11 PL D0 D1 D2 D3 12 CPU 5 COUNTER TCD CPD 13 4 11 15 1 10 9 CPU 5 12 TCU MR 14 FLIP-FLOPS CPD 4 13 TCD 14 3 2 6 7 Q0 Q1 Q2 Q3 3 2 6 7 001aag405 MR Q0 Q1 Q2 Q3 001aag409 Fig. 1. Functional diagram Fig. 2. Logic symbol CTR4 11 C3 5 2+ G1 4 1- G2 14 R 15 3 3D 1 2 10 6 9 7 13 2CT = 0 12 1CT = 15 001aag410 Fig. 3. IEC logic symbol 74HC HCT193 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 7 8 September 2021 2 / 24