74HCT640N

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT640 Octal bus transceiver 3-state inverting March 1988 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Octal bus transceiver 3-state inverting 74HC/HCT640 FEATURES GENERAL DESCRIPTION Octal bidirectional bus interface The 74HC/HCT640 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL Inverting 3-state outputs (LSTTL). They are specified in compliance with JEDEC Output capability: bus driver standard no. 7A. I category: MSI CC The 74HC/HCT640 are octal transceivers featuring inverting 3-state bus compatible outputs in both send and receive directions. The 640 features an output enable (OE) input for easy cascading and a send/receive (DIR) for direction control. OE controls the outputs so that the buses are effectively isolated. The 640 is similar to the 245 but has inverting outputs. QUICK REFERENCE DATA GND = 0 V T =25 C t =t =6ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t t / propagation delay C = 15 pF V = 5 V 9 9 ns PHL PLH L CC A to B n n B to A n n C input capacitance 3.5 3.5 pF I C input/output capacitance 10 10 pF I/O C power dissipation capacitance notes 1 and 2 35 35 pF PD per transceiver Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. March 1988 2