74LV74N,112 NXP

74LV74 Dual D-type flip-flop with set and reset positive-edge trigger Rev. 4 9 December 2015 Product data sheet 1. General description The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features and benefits Wide supply voltage range from 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Direct interface with TTL levels (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from 40 Cto+85 C and from 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV74D 40 C to +125 C SO14 plastic small outline package 14 leads body width 3.9 mm SOT108-1 74LV74DB 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads body width SOT337-1 5.3 mm 74LV74PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads body SOT402-1 width 4.4 mm 74LV74 Nexperia Dual D-type flip-flop with set and reset positive-edge trigger 4. Functional diagram 6 6 6 4 5 &3 )) &3 6 4 5 5 DDD DDD Fig 1. Logic symbol Fig 2. IEC logic symbol 6 4 4 3 4 6 4 4 3 4 DDD Fig 3. Functional diagram 74LV74 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 4 9 December 2015 2 of 18 5 5 4 )) &3 & 6 5 5 4 )) &3 & 6 5 5 4 & 4 &3 4 4 6 &