74LV74PW,118 Nexperia

74LV74 Dual D-type flip-flop with set and reset positive-edge trigger Rev. 5 24 March 2021 Product data sheet 1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess V . CC 2. Features and benefits Wide supply voltage range from 1.0 V to 5.5 V Optimized for low voltage applications from 1.0 V to 3.6 V CMOS low power dissipation Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Direct interface with TTL levels (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV74D -40 C to +125 C SO14 plastic small outline package 14 leads body width 3.9 mm SOT108-1 74LV74PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mmNexperia 74LV74 Dual D-type flip-flop with set and reset positive-edge trigger 4. Functional diagram 4 S 5 4 10 3 C1 1SD 2SD 2 1D SD 6 2 1D 1Q 5 1 D Q R 12 2D 2Q 9 3 1CP CP FF 11 2CP 10 9 S 1Q 6 11 Q C2 2Q 8 RD 12 2D 1RD 2RD 8 13 R 1 13 aaa-008836 aaa-008837 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 4 1SD SD 2 1D 1Q 5 D Q 3 1CP CP FF1 1Q 6 Q RD 1 1RD 10 2SD SD 12 2D 2Q 9 D Q 11 2CP CP FF2 2Q 8 Q RD 13 2RD aaa-008838 Fig. 3. Functional diagram 74LV74 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 24 March 2021 2 / 15