GTL2003 8-bit bidirectional low voltage translator Rev. 2 3 July 2012 Product data sheet 1. General description The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2003 provides eight NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The device allows bidirectional voltage translations between 0.8 V and 5.0 V without use of a direction pin. Voltage translation below 0.8 V can be achieved when properly biased. For more information, refer to application note AN11127 (Ref. 1). When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to V DD1 by the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user, without the need for directional control. All transistors have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the transistors is symmetrical. Because all transistors in the device are identical, SREF and DREF can be located on any of the other eight matched Sn/Dn transistors, allowing for easier board layout. The translator s transistors provide excellent ESD protection to lower voltage devices and at the same time protect less ESD-resistant devices. 2. Features and benefits 8-bit bidirectional low voltage translator Allows voltage level translation between 0.8 V, 0.9 V, 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V buses which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels Provides bidirectional voltage translation with no direction pin Low 6.5 ON-state resistance (R ) between input and output pins (Sn/Dn) on Supports hot insertion No power supply required: will not latch up 5 V tolerant inputs Low standby current Flow-through pinout for ease of printed-circuit board trace routing ESD protection exceeds 2000 V HBM per JESD22-A114, and 1000 V CDM per JESD22-C101 Packages offered: TSSOP20, DHVQFN20GTL2003 NXP Semiconductors 8-bit bidirectional low voltage translator 3. Applications Any application that requires bidirectional or unidirectional voltage level translation from any voltage from 0.8 V to 5.0 V to any voltage from 0.8 V to 5.0 V The open-drain construction with no direction pin is ideal for bidirectional low voltage 2 (for example, 0.8 V, 0.9 V, 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I C-bus port 2 translation to the normal 3.3 V and/or 5.0 V I C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels. 4. Ordering information Table 1. Ordering information Type number Package Name Description Version GTL2003BQ DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mm GTL2003PW TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 4.1 Ordering options Table 2. Ordering options Type number Topside mark Temperature range GTL2003BQ 2003 40 C to +85 C GTL2003PW GTL2003 40 C to +85 C 5. Functional diagram DREF GREF D1 D8 SREF S1 S8 002aac641 Fig 1. Functional diagram GTL2003 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 3 July 2012 2 of 24