GTL2006PW,118

INTEGRATED CIRCUITS GTL2006 13-bit GTL/GTL/GTL+ to LVTTL translator Product data 2004 Jun 21 Supersedes data of 2003 Dec 18 Philips SemiconductorsPhilips Semiconductors Product data 13-bit GTL/GTL/GTL+ to LVTTL translator GTL2006 FEATURES PIN CONFIGURATION Operates as a GTL/GTL/GTL+ to LVTTL sampling receiver or V 1 28 V REF CC LVTTL to GTL/GTL/GTL+ driver 1AO 1BI 2 27 3.0 V to 3.6 V operation 2AO 3 26 2BI LVTTL I/O not 5 V tolerant 5A 4 25 7BO1 Series termination on the LVTTL outputs of 30 6A 5 24 7BO2 ESD protection exceeds 2000 V HBM per JESD22-A114, 8AI 6 23 8BO 200 V MM per JESD22-A115 and 250 V CDM per JESD22-C101 11BI 7 22 11BO Latch-up testing is done to JESDEC Standard JESD78 which 11A 8 21 5BI exceeds 500 mA 9BI 9 20 6BI Package offered: TSSOP28 3AO 10 19 3BI 4AO 11 18 4BI DESCRIPTION 10AI1 12 17 10BOI The GTL2006 is a 13-bit translator to interface between the 3.3 V LVTTL chip set I/O and the Xeon processor GTL/GTL/GTL+ I/O. 10AI2 13 16 10BO2 The GTL2006 is designed for platform health management in dual GND 14 15 9AO processor applications. SW01091 Figure 1. Pin configuration PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 1 V GTL reference voltage REF 26, 8, Data inputs/outputs nAn 1013, 15 (LVTTL) 7, 9, 16, Data inputs/outputs nBn 1727 (GTL/GTL/GTL+) 14 GND Ground (0 V) 28 V Positive supply voltage CC QUICK REFERENCE DATA TYPICALTYPICAL CONDITIONSCONDITIONS SYMBOLSYMBOL PPARAMETERARAMETER UNITUNIT T = 25 C amb B to A A to B t Propagation delay PLH C = 50 pF V = 3.3 V 5.5 5.5 ns L CC t An to Bn or Bn to An PHL C I/O pin capacitance Outputs disabled V = 0 V or 3.0 V 7.8 4.5 pF I/O I/O ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DWG NUMBER 28-Pin Plastic TSSOP 40 C to +85 C GTL2006PW GTL2006 SOT361-1 Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging. 2 2004 Jun 21