HEF4015B
Dual 4-bit static shift register
Rev. 8 21 November 2011 Product data sheet
1. General description
The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel
converter). Each shift register has a serial data input (D), a clock input (CP), four fully
buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input
(MR). Information present on D is shifted to the first register position, and all the data in
the register is shifted one position to the right on the LOW-to-HIGH transition of CP. A
HIGH on MR clears the register and forces Q0 to Q3 to LOW, independent of CP and D.
The clock inputs Schmitt trigger action makes the input highly tolerant of slower clock rise
and fall times.
It operates over a recommended V power supply range of 3 V to 15 V referenced to V
DD SS
(usually ground). Unused inputs must be connected to V , V , or another input.
DD SS
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C.
Complies with JEDEC standard JESD 13-B
3. Applications
Serial-to-parallel converter
Buffer stores
General purpose register
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C.
Type number Package
Name Description Version
HEF4015BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4015BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
5. Functional diagram
1Q0 5
7 1D
1Q1 4
SHIFT
REGISTER
1Q2 3
4 BITS
9 1CP
1Q3 10
6 1MR
2Q0 13
15 2D
2Q1 12
SHIFT
REGISTER
2Q2 11
4 BITS
1 2CP
2Q3 2
14 2MR
001aae560
Fig 1. Functional diagram
Q0 Q1 Q2 Q3
D DQ DQ DQ DQ
FF 1 FF 2 FF 3 FF 4
CP CP CP CP
CD CD CD CD
CP
MR
001aae562
Fig 2. Logic diagram for one register
HEF4015B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 21 November 2011 2 of 15