HEF40174BT,653 NXP

HEF40174B Hex D-type flip-flop Rev. 7 21 November 2011 Product data sheet 1. General description The HEF40174B is a hex edge-triggered D-type flip-flop with six data inputs (D0 to D5), a clock input (CP), an overriding asynchronous master reset input (MR), and six buffered outputs (Q0 to Q5). Information on D0 to D5 is transferred to Q0 to Q5 on the LOW-to-HIGH transition of CP if MR is HIGH. When LOW, MR resets all flip-flops (Q0 to Q5 = LOW) independent of CP and D0 to D5. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Applications Shift registers Buffer/storage register Pattern generator 4. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number Package Name Description Version HEF40174BP DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 HEF40174BT SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1HEF40174B NXP Semiconductors Hex D-type flip-flop 5. Functional diagram 3 4 6 11 13 14 D0 D1 D2 D3 D4 D5 D Q D Q D Q D Q D Q D Q FF1 FF2 FF3 FF4 FF5 FF6 CP CP CP CP CP CP CD CD CD CD CD CD CP 9 MR 1 Q0 Q1 Q2 Q3 Q4 Q5 2 5 7 10 12 15 001aae565 Fig 1. Functional diagram D0 D1 D2 D3 D4 D5 D D D D D D FF1 FF2 FF3 FF4 FF5 FF6 CP Q CP Q CP Q CP Q CP Q CP Q CD CD CD CD CD CD CP MR Q0 Q1 Q2 Q3 Q4 Q5 001aae567 Fig 2. Logic diagram HEF40174B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 21 November 2011 2 of 14