HEF4020B 14-stage binary counter Rev. 8 18 November 2011 Product data sheet 1. General description The HEF4020B is a 14-stage binary counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to Q13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the device is its high speed (typ. 35 MHz at V =15V). DD It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits High speed operation Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number Package Name Description Version HEF4020BP DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 HEF4020BT SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1HEF4020B NXP Semiconductors 14-stage binary counter 4. Functional diagram 10 CP T 14-STAGE COUNTER 11 MR C D 9 7 5 4 6 13 12 14 15 1 2 3 Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aad722 Fig 1. Functional diagram CTR14 Q0 9 09 + 10 Q3 7 7 11 CT Q4 5 5 Q5 4 4 10 CP Q6 6 6 Q7 13 13 CT Q8 12 12 Q9 14 14 11 MR Q10 15 15 Q11 1 1 Q12 2 2 Q13 3 13 3 001aad723 001aad724 Fig 2. Logic symbol Fig 3. IEC Logic symbol Q Q Q Q Q Q Q FF FF FF FF FF FF FF 0 1 2 3 4 5 6 CP T T T T T T T Q Q Q Q Q Q Q RD RD RD RD RD RD RD MR Q0 Q3 Q4 Q5 Q6 Q Q Q Q Q Q Q FF FF FF FF FF FF FF 7 8 9 10 11 12 13 T T T T T T T Q Q Q Q Q Q Q RD RD RD RD RD RD RD Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aad725 Fig 4. Logic diagram HEF4020B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 8 18 November 2011 2 of 14