HEF4028BPN

HEF4028B BCD to decimal decoder Rev. 8 17 November 2011 Product data sheet 1. General description The HEF4028B is a 4-bit BCD to decimal decoder, a 4-bit BCO to octal decoder with active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer. The outputs are fully buffered for best performance. When used as a BCD to decimal decoder a 1-2-4-8 BCD code applied to inputs A0 to A3 causes the selected output to be HIGH. The other nine outputs will be LOW. To use the HEF4028B as a BCO to octal decoder, input A3 is an active LOW enable pin and outputs Y8 and Y9 are not used. A 1-2-4 BCO code applied to inputs A0 to A2 causes the selected output (Y0 to Y7) to be HIGH. The other seven outputs will be LOW. When A3 is HIGH outputs (Y0 to Y7) will be forced LOW. When used as an 8-output (Y0 to Y7) inverting demultiplexer A0 to A2 are used as address inputs and A3 is the data input. Outputs Y8 and Y9 are not used. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number Package Name Description Version HEF4028BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4028BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1HEF4028B NXP Semiconductors BCD to decimal decoder 4. Functional diagram A0 A1 A2 A3 10 13 12 11 DECODER 3 14 2 15 1 6 7 4 9 5 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 001aae598 Fig 1. Functional diagram Y0 Y1 A0 Y2 Y3 A1 Y4 Y5 A2 Y6 Y7 A3 Y8 Y9 001aae600 Fig 2. Logic diagram HEF4028B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 8 17 November 2011 2 of 13