LPC11Axx 32-bit ARM Cortex-M0 microcontroller up to 32 kB flash, 8 kB SRAM, 4 kB EEPROM configurable analog/mixed-signal Rev. 3 7 September 2012 Product data sheet 1. General description The LPC11Axx are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC11Axx operate at CPU frequencies of up to 50 MHz. Analog/mixed-signal subsystems can be configured by software from interconnected digital and analog peripherals. The digital peripherals on the LPC11Axx include up to 32 kB of flash memory, up to 4 kB 2 of EEPROM data memory, up to 8 kB of SRAM data memory, a Fast-mode Plus I C-bus interface, a RS-485/EIA-485 USART, two SSP controllers, four general purpose counter/timers, and up to 42 general purpose I/O pins. Analog peripherals include a 10-bit ADC, a 10-bit DAC, an analog comparator, a temperature sensor, an internal voltage reference, and UnderVoltage LockOut (UVLO) protection. 2. Features and benefits System: ARM Cortex-M0 processor, running at frequencies of up to 50 MHz. ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). Serial Wire Debug (SWD) JTAG boundary scan. System tick timer. Memory: Up to 32 kB on-chip flash program memory. Up to 4 kB on-chip EEPROM data memory byte erasable and byte programmable. Up to 8 kB SRAM data memory. 16 kB boot ROM. In-System Programming (ISP) for flash and In-Application Programming (IAP) for flash and EEPROM via on-chip bootloader software. 2 Includes ROM-based 32-bit integer division and I C-bus driver routines. Digital peripherals: Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode.LPC11Axx NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Up to 16 pins are configurable with a digital input glitch filter for removing glitches with widths of 10 ns or less and two pins are configurable for 50 ns glitch filters. GPIO pins can be used as edge and level sensitive interrupt sources. High-current source output driver (20 mA) on one pin (PIO0 21). High-current sink driver (20 mA) on true open-drain pins (PIO0 2 and PIO0 3). Four general purpose counter/timers with a total of up to 16 capture inputs and 14 match outputs. Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal low-power WatchDog Oscillator (WDOsc). Analog peripherals: 10-bit ADC with input multiplexing among 8 pins. 10-bit DAC with flexible conversion triggering. Highly flexible analog comparator with a programmable voltage reference. Integrated temperature sensor. Internal voltage reference. UnderVoltage Lockout (UVLO) protection against power-supply droop below 2.4 V. Serial interfaces: USART with fractional baud rate generation, internal FIFO, support for RS-485/9-bit mode and synchronous mode. Two SSP controllers with FIFO and multi-protocol capabilities. Support data rates of up to 25 Mbit/s. 2 2 I C-bus interface supporting the full I C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode. Clock generation: Crystal Oscillator (SysOsc) with an operating range of 1 MHz to 25 MHz. 12 MHz internal RC Oscillator (IRC) trimmed to 1% accuracy that can optionally be used as a system clock. Internal low-power, Low-Frequency Oscillator (LFOsc) with programmable frequency output. Clock input for external system clock (25 MHz typical). PLL allows CPU operation up to the maximum CPU rate with the IRC, the external clock, or the SysOsc as clock sources. Clock output function with divider that can reflect the SysOsc, the IRC, the main clock, or the LFOsc. Power control: Supports one reduced power mode: The ARM Sleep mode. Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call. Processor wake-up from reduced power mode using any interrupt. Power-On Reset (POR). Brown-Out Detect (BOD) with two programmable thresholds for interrupt and one hardware controlled reset trip point. POR and BOD are always enabled for rapid UVLO protection against power supply voltage droop below 2.4 V. Unique device serial number for identification. LPC11AXX All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 7 September 2012 2 of 82