LPC5411x 32-bit ARM Cortex-M4/M0+ MCU 192 KB SRAM 256 KB flash, Crystal-less USB operation, DMIC subsystem, Flexcomm Interface, 32-bit counter/ timers, SCTimer/PWM, 12-bit 5.0 Msamples/sec ADC, Temperature sensor Rev. 2.6 3 September 2020 Product data sheet 1. General description The LPC5411x are ARM Cortex-M4 based microcontrollers for embedded applications. These devices include an ARM Cortex-M0+ coprocessor, up to 192 KB of on-chip SRAM, up to 256 KB on-chip flash, full-speed USB device interface with Crystal-less operation, a DMIC subsystem with PDM microphone interface and I2S, five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), eight flexible serial communication peripherals 2 (each of which can be a USART, SPI, or I C interface), and one 12-bit 5.0 Msamples/sec ADC, and a temperature sensor. The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point unit is integrated in the core. The ARM Cortex-M0+ coprocessor is an energy-efficient and easy-to-use 32-bit core which is code and tool-compatible with the Cortex-M4 core. The Cortex-M0+ coprocessor offers up to 150 MHz performance with a simple instruction set and reduced code size. 2. Features and benefits Dual processor cores: ARM Cortex-M4 and ARM Cortex-M0+. Both cores operate up to a maximum frequency of 150 MHz. ARM Cortex-M4 core (version r0p1): ARM Cortex-M4 processor, running at a frequency of up to 150 MHz. Floating Point Unit (FPU) and Memory Protection Unit (MPU). ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input with a selection of sources. Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators, and four watch points. Includes Serial Wire Output for enhanced debug capabilities. System tick timer. NXP Semiconductors LPC5411x 32-bit ARM Cortex-M4/M0+ microcontroller ARM Cortex-M0+ core ARM Cortex-M0+ processor, running at a frequency of up to 150 MHz (uses the same clock as Cortex-M4) with a single-cycle multiplier and a fast single-cycle I/O port. ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input with a selection of sources. Serial Wire Debug with four breakpoints and two watch points. System tick timer. On-chip memory: Up to 256 KB on-chip flash program memory with flash accelerator and 256 byte page erase and write. Up to 192 KB total SRAM consisting of 160 KB contiguous main SRAM and an additional 32 KB SRAM on the I&D buses. ROM API support: Flash In-Application Programming (IAP) and In-System Programming (ISP). ROM-based USB drivers (HID, CDC, MSC, and DFU). Flash updates via USB is supported. 2 Supports booting from valid user code in flash, USART, SPI, and I C. Legacy, Single, and Dual image boot. Serial interfaces: Flexcomm Interface contains eight serial peripherals. Each can be selected by 2 software to be a USART, SPI, or I C interface. Two Flexcomm Interfaces also 2 include an I S interface. Each Flexcomm Interface includes a FIFO that supports 2 USART, SPI, and I S if supported by that Flexcomm Interface. A variety of clocking options are available to each Flexcomm Interface and include a shared fractional baud-rate generator. 2 I C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true 2 I C pads also support high speed mode (3.4 Mbit/s) as a slave. USB 2.0 full-speed device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode using software library. See Technical note TN00031 for more details. Digital peripherals: DMA controller with 20 channels and 20 programmable triggers, able to access all memories and DMA-capable peripherals. Up to 48 General-Purpose Input/Output (GPIO) pins. Most GPIOs have configurable pull-up/pull-down resistors, programmable open-drain mode, and input inverter. GPIO registers are located on the AHB for fast access. Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling or both input edges. Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states. CRC engine. LPC5411x All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 2.6 3 September 2020 2 of 105