NXP Semiconductors Document Number: PF3001 Rev. 4.0, 8/2017 Data sheet: Advance Information Power management integrated PF3001 circuit (PMIC) for i.MX 7 and i.MX 6 SoloLite/SoloX/UltraLite processors The PF3001 is a SMARTMOS power management integrated circuit (PMIC) POWER MANAGEMENT designed specifically for always ON applications with the NXP i.MX 7 and i.MX 6 SoloLite/SoloX/UltraLite application processors. With up to three buck converters, six linear regulators, RTC supply, and coin-cell charger, the PF3001 can provide power for a complete system, including applications processors, memory, and system peripherals. Features: EP SUFFIX ES SUFFIX Three adjustable high efficiency buck regulators: 2.75 A, 1.5 A, 1.25 A 98ASA00719D 98ASA00933D Selectable modes: PWM, PFM, APS 48 QFN 7.0 X 7.0 48 QFN 7.0 X 7.0 Programmable output voltage, PWM switching frequency, current limit Applications: Six adjustable general purpose linear regulators IPTV Input voltage range: 2.8 V to 4.5 V or 3.7 V to 5.5 V Set top boxes 2 I C control POS terminals Coin cell charger and always ON RTC supply Industrial control -40 C to +125 C Operating Junction Temperature Medical monitoring Home automation/security/energy management i.MX PF3001 DDR MEMORY DDR MEMORY Switching regulators INTERFACE SW3 0.90 1.65 V, 1.5A Processor ARM Core SW1 0.70 3.30 V, 2.75A Processor SOC SW2 1.50 1.85 V External AMP or 2.5 -3.3 V, 1.25A Microphones SATA - FLASH Speakers SD-MMC/ SATA NAND - NOR NAND Mem. HDD Interfaces RESETBMCU Audio PWRON Codec Parallel control / GPIOs SD VSEL INTB Li CELL 2 2 Charger I C I C Sensors Linear regulators Camera Camera VLDO1 1.8 3.3 V, 100mA GPS MIPI VLDO2 0.8 1.55 V, 250mA WAM Micro PCIe GPS/MIPI VCC SD 1.8 1.85 V or 2.85 3.3 V, 100mA HDMI LVDS Display V33 2.85 -3.3 V, 350mA USB Ethernet CAN VLDO3 1.8 3.3 V, 100mA VLDO4 1.8 -3.3 V, 350mA Cluster/ Front USB Rear Seat Rear USB HUD POD Infotainment POD Main Supply COINCELL 2.8 - 5.5 V Figure 1. PF3001 simplified application diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. NXP B.V. 2017.Table of Contents 1 Orderable parts 3 2 General description . 4 3 Internal Block Diagram . 6 4 Pin connections 7 4.1 Pinout diagram . 7 4.2 Pin definitions 8 5 General product characteristics . 10 5.1 Maximum ratings . 10 5.2 Thermal characteristics 11 5.3 Current consumption 12 5.4 Electrical characteristics . 13 6 Functional description and application information 25 6.1 Introduction . 25 6.2 Power generation 25 6.3 Functional description . 27 6.3.1 Control logic and interface signals 27 6.3.2 Start-up . 28 6.3.4 16 MHz and 32 kHz clocks 29 6.3.5 Optional front-end input LDO regulator . 30 6.3.6 Internal core voltages 31 6.3.7 Buck regulators . 31 6.3.8 LDO regulators description 36 6.3.9 VSNVS LDO/switch . 39 6.4 Power dissipation 41 6.5 Modes of operation . 42 6.5.1 State diagram .42 6.5.2 State machine flow summary .43 6.5.3 Performance characteristics curves 43 6.6 Control interface I2C block description 46 6.6.1 I2C device ID .46 6.6.2 I2C operation .46 6.6.3 Interrupt handling 47 6.6.4 Interrupt bit summary .47 6.6.5 Specific registers .52 6.6.6 Register map 75 7 Typical applications 79 7.1 Application diagram . 79 8 Bill of materials 80 9 Thermal information 82 9.1 Rating data . 82 9.2 Estimation of junction temperature . 82 10 Packaging 83 10.1Packaging dimensions 83 11 Revision history . 89 PF3001 2 NXP Semiconductors