MC33910G5AC/MC3433910G5AC NXP Semiconductors Document Number: MC33911 Rev. 10.0, 7/2016 Technical Data LIN system basis chip with DC motor 33911 pre-driver The 33911G5/BAC is a SMARTMOS Serial Peripheral Interface (SPI) controlled System Basis Chip (SBC), combining many frequently used functions in an MCU based system, plus a Local Interconnect Network (LIN) transceiver. The 33911 SYSTEM BASIS CHIP WITH LIN has a 5.0 V, 50 mA/60 mA low dropout regulator with full protection and reporting features. The device provides full SPI readable diagnostics and a selectable timing watchdog for detecting errant operation. The LIN Protocol Specification 2.0 and 2.1 compliant LIN transceiver has waveshaping circuitry which can be disabled for higher data rates. One 50 mA/60 mA high-side switch and two 150 mA/160 mA low-side switches with output protection are available. All outputs can be pulse-width modulated (PWM). Two high-voltage inputs are available for use in contact monitoring, or as external wake-up inputs. These inputs can be used as high-voltage Analog Inputs. The voltage on these pins is divided by a selectable ratio and available via an analog multiplexer. The 33911 has three main operating modes: Normal (all functions available), AC SUFFIX (Pb-FREE) Sleep (V off, wake-up via LIN, wake-up inputs (L1, L2), cyclic sense, and 98ASH70029A DD 32-PIN LQFP forced wake-up), and Stop (V on with limited current capability, wake-up via DD CS, LIN bus, wake-up inputs, cyclic sense, forced wake-up, and external reset). The 33911 is compatible with LIN Protocol Specification 2.0, 2.1, and SAEJ2602-2. Features Applications Full-duplex SPI interface at frequencies up to 4.0 MHz Window lift LIN transceiver capable of up to 100 kbps with wave shaping Mirror switch One 50 mA/60 mA high-side and two 150 mA/60 mA low-side protected Door lock switches Sunroof Two high-voltage analog/logic Inputs Light control Configurable window watchdog 5.0 V low drop regulator with fault detection and low-voltage reset (LVR) circuitry 33911 V BAT VS1 VSENSE HS1 VS2 L1 L2 LIN INTERFACE LIN VDD PWMIN LS1 ADOUT0 M LS2 MCU MOSI MISO SCLK CS WDCONF RXD TXD IRQ RST Figure 1. 33911 simplified application diagram 2016 NXP B.V. LGND PGND AGND1 Orderable parts The 33911G5 data sheet is within MC33911G5 product specifications - page 3 to page 52. The 33911BAC data sheet is within MC33911BAC product specifications - page 53 to page 100. Table 1. Orderable part variations Device Temperature Package Generation MC33911G5AC/R2 - 40 C to 125 C Increase ESD GUN IEC61000-4-2 (gun test contact with 150 pF, 330 test conditions) performance to achieve 6.0 kV min on the LIN pin. Immunity against ISO7637 pulse 3b 2.5 Reduce EMC emission level on LIN MC34911G5AC/R2 - 40 C to 85 C Improve EMC immunity against RF target new specification including 3 32-LQFP x 68 pF Comply with J2602 conformance test MC33911BAC/R2 - 40 C to 125 C 2.0 Initial release MC34911BAC/R2 - 40 C to 85 C 33911 2 NXP Semiconductors