MCF52230CAL60

Freescale Semiconductor Document Number: MCF52235 Rev. 10, 3/2011 Data Sheet: Technical Data MCF52235 LQFP-80 LQFP-112 MCF52235 ColdFire 14mm x 14mm 20mm_x_20mm Microcontroller Data Sheet MAPBGA-121 Supports MCF52230, MCF52231, 12mm_x_12mm MCF52232, MCF52233, MCF52234, MCF52235, and MCF52236 The MCF52235 is a member of the ColdFire family of Two 16-bit periodic interrupt timers (PITs) reduced instruction set computing (RISC) microcontrollers. Real-time clock (RTC) module This document provides an overview of the MCF52235 Programmable software watchdog timer microcontroller family, focusing on its highly integrated and Two interrupt controllers providing every peripheral with a diverse feature set. unique selectable-priority interrupt vector plus seven external interrupts with fixed levels/priorities This 32-bit device is based on the Version 2 ColdFire core Clock module with support for crystal or external oscillator operating at a frequency up to 60 MHz, offering high and integrated phase-locked loop (PLL) performance and low power consumption. On-chip memories Test access/debug port (JTAG, BDM) connected tightly to the processor core include up to 256 Kbytes of Flash and 32 Kbytes of static random access memory (SRAM). On-chip modules include: V2 ColdFire core providing 56 Dhrystone 2.1 MIPS @ 60 MHz executing out of on-chip Flash memory using enhanced multiply accumulate (EMAC) and hardware divider Enhanced Multiply Accumulate Unit (EMAC) and hardware divide module Cryptographic Acceleration Unit (CAU) coprocessor Fast Ethernet Controller (FEC) On-chip Ethernet Transceiver (EPHY) FlexCAN controller area network (CAN) module Three universal asynchronous/synchronous receiver/transmitters (UARTs) 2 Inter-integrated circuit (I C) bus controller Queued serial peripheral interface (QSPI) module Eight-channel 10- or 12-bit fast analog-to-digital converter (ADC) Four channel direct memory access (DMA) controller Four 32-bit input capture/output compare timers with DMA support (DTIM) Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width modulation (PWM) and pulse accumulation Eight/Four-channel 8/16-bit pulse width modulation timers (two adjacent 8-bit PWMs can be concatenated to form a single 16-bit timer) Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Freescale Semiconductor, Inc., 2011. All rights reserved.Table of Contents 1 MCF52235 Family Configurations . . . . . . . . . . . . . . . . . . . . . .3 Figure 14.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . 44 1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 15.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . 45 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 16.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . 45 1.3 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 17.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.4 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 18.Real-Time Trace AC Timing. . . . . . . . . . . . . . . . . . . . 46 1.5 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 19.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . . 46 1.6 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . .22 List of Tables 1.7 Queued Serial Peripheral Interface (QSPI). . . . . . . . . .23 Table 1. MCF52235 Family Configurations . . . . . . . . . . . . . . . . . 3 1.8 Fast Ethernet Controller EPHY Signals . . . . . . . . . . . .23 2 Table 2. Orderable Part Number Summary. . . . . . . . . . . . . . . . 13 1.9 I C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 3. Pin Functions by Primary and Alternate Purpose . . . . 17 1.10 UART Module Signals. . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 4. Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.11 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 5. PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . 22 1.12 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table 6. Mode Selection Signals. . . . . . . . . . . . . . . . . . . . . . . . 22 1.13 General Purpose Timer Signals . . . . . . . . . . . . . . . . . .25 Table 7. External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . 22 1.14 Pulse Width Modulator Signals . . . . . . . . . . . . . . . . . . .25 Table 8. Queued Serial Peripheral Interface (QSPI) Signals. . . 23 1.15 Debug Support Signals. . . . . . . . . . . . . . . . . . . . . . . . .25 Table 9. Fast Ethernet Controller (FEC) Signals . . . . . . . . . . . . 23 1.16 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . .27 2 Table 10.I C I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.17 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . .27 Table 11.UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . 24 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 12.DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 13.ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table 14.GPT Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .32 Table 15.PWM Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4 Phase Lock Loop Electrical Specifications . . . . . . . . . .33 Table 16.Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .35 Table 17.EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . 27 2.6 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2 Table 18.Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . 27 2.7 I C Input/Output Timing Specifications . . . . . . . . . . . . .36 Table 19.Absolute Maximum Ratings, . . . . . . . . . . . . . . . . . . . 29 2.8 EPHY Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 20.Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 30 2.9 Analog-to-Digital Converter (ADC) Parameters . . . . . .40 Table 21.ESD Protection Characteristics . . . . . . . . . . . . . . . . . . 31 2.10 DMA Timers Timing Specifications . . . . . . . . . . . . . . . .42 Table 22.DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . 32 2.11 EzPort Electrical Specifications . . . . . . . . . . . . . . . . . .42 Table 23.Active Current Consumption Specifications. . . . . . . . . 33 2.12 QSPI Electrical Specifications. . . . . . . . . . . . . . . . . . . .43 Table 24.Current Consumption Specifications in 2.13 JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . .44 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.14 Debug AC Timing Specifications. . . . . . . . . . . . . . . . . .46 Table 25.PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . 33 3 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .47 Table 26.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.1 80-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .47 Table 27.Reset and Configuration Override Timing . . . . . . . . . . 35 3.2 112-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . .48 2 Table 28.I C Input Timing Specifications between 3.3 121 MAPBGA Package. . . . . . . . . . . . . . . . . . . . . . . . .51 I2C_SCL and I2C_SDA . . . . . . . . . . . . . . . . . . . . . . . . 36 4 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2 Table 29. I C Output Timing Specifications between List of Figures I2C_SCL and I2C_SDA . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 1.MCF52235 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 4 Table 30.EPHY Timing Parameters . . . . . . . . . . . . . . . . . . . . . . 38 Figure 2.80-pin LQFP Pin Assignments . . . . . . . . . . . . . . . . . . 14 Table 31.10BASE-T SQE (Heartbeat) Timing Parameters . . . . 38 Figure 3.112-pin LQFP Pin Assignments . . . . . . . . . . . . . . . . . 15 Table 32.10BASE-T Jab and Unjab Timing Parameters . . . . . . 39 Figure 4.121 MAPBGA Pin Assignments . . . . . . . . . . . . . . . . . 16 Table 33.10BASE-T Transceiver Characteristics . . . . . . . . . . . . 40 Figure 5.Suggested Connection Scheme for Power and Ground 28 Table 34.100BASE-TX Transceiver Characteristics . . . . . . . . . . 40 Figure 6.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 35.ADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 7.RSTI and Configuration Override Timing . . . . . . . . . . 36 Table 36.Timer Module AC Timing Specifications . . . . . . . . . . . 42 2 Figure 8.I C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . 37 Table 37.EzPort Electrical Specifications . . . . . . . . . . . . . . . . . . 42 Figure 9.EPHY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 38.QSPI Modules AC Timing Specifications. . . . . . . . . . . 43 Figure 10.10BASE-T SQE (Heartbeat) Timing . . . . . . . . . . . . . 39 Table 39.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 44 Figure 11.10BASE-T Jab and Unjab Timing . . . . . . . . . . . . . . . 39 Table 40.Debug AC Timing Specification . . . . . . . . . . . . . . . . . . 46 Figure 12.Equivalent Circuit for A/D Loading. . . . . . . . . . . . . . . 42 Table 41.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 13.QSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10 2 Freescale Semiconductor