Freescale Semiconductor Document Number: MCF5329DS Rev. 5, 11/2008 Data Sheet: Technical Data MCF5329 MAPBGA256 MAPBGA196 17mm x 17mm 15mm x 15mm MCF532x ColdFire Microprocessor Data Sheet Features Version 3 ColdFire variable-length RISC processor core System debug support JTAG support for system level board testing On-chip memories 16-Kbyte unified write-back cache 32-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC, LCD controller, and USB host and OTG) Power management Liquid Crystal Display Controller (LCDC) Embedded Voice-over-IP (VoIP) system solution SDR/DDR SDRAM Controller Universal Serial Bus (USB) Host Controller Universal Serial Bus (USB) On-the-Go (OTG) controller Synchronous Serial Interface (SSI) Fast Ethernet Controller (FEC) Cryptography Hardware Accelerators FlexCAN Module Three Universal Asynchronous Receiver Transmitters (UARTs) 2 I C Module Queued Serial Peripheral Interface (QSPI) Pulse Width Modulation (PWM) module Real Time Clock Four 32-bit DMA Timers Software Watchdog Timer Four Periodic Interrupt Timers (PITs) Phase Locked Loop (PLL) Interrupt Controllers (x2) DMA Controller FlexBus (External Interface) Chip Configuration Module (CCM) Reset Controller General Purpose I/O interface Freescale Semiconductor, Inc., 2008. All rights reserved.Table of Contents 1MCF532x Family Comparison .3 5.7.2 DDR SDRAM AC Timing Characteristics . 25 2 Ordering Information .4 5.8 General Purpose I/O Timing 28 3 Hardware Design Considerations .5 5.9 Reset and Configuration Override Timing 29 3.1 PLL Power Filtering .5 5.10 LCD Controller Timing Specifications . 30 3.2 USB Power Filtering 5 5.11 USB On-The-Go . 33 3.3 Supply Voltage Sequencing and Separation Cautions 5 5.12 ULPI Timing Specification 33 3.3.1 Power Up Sequence 5 5.13 SSI Timing Specifications 33 2 3.3.2 Power Down Sequence 6 5.14 I C Input/Output Timing Specifications 35 4 Pin Assignments and Reset States .6 5.15 Fast Ethernet AC Timing Specifications . 37 4.1 Signal Multiplexing .6 5.15.1 MII Receive Signal Timing 37 4.2 Pinout256 MAPBGA .14 5.15.2 MII Transmit Signal Timing 37 4.3 Pinout196 MAPBGA .15 5.15.3 MII Async Inputs Signal Timing 38 5 Electrical Characteristics 15 5.15.4 MII Serial Management Channel Timing . 38 5.1 Maximum Ratings .16 5.16 32-Bit Timer Module Timing Specifications . 39 5.2 Thermal Characteristics 17 5.17 QSPI Electrical Specifications . 39 5.3 ESD Protection .18 5.18 JTAG and Boundary Scan Timing 40 5.4 DC Electrical Specifications .18 5.19 Debug AC Timing Specifications . 42 5.5 Oscillator and PLL Electrical Characteristics 19 6 Current Consumption 42 5.6 External Interface Timing Characteristics .20 7 Package Information . 45 5.6.1 FlexBus .21 7.1 Package Dimensions256 MAPBGA . 45 5.7 SDRAM Bus .23 7.2 Package Dimensions196 MAPBGA . 46 5.7.1 SDR SDRAM AC Timing Characteristics 23 8 Revision History 47 MCF532x ColdFire Microprocessor Data Sheet, Rev. 5 2 Freescale Semiconductor