MFRC50001T/0FE,112 NXP

MFRC500 Highly Integrated ISO/IEC 14443 A Reader IC Rev. 3.3 15 March 2010 Product data sheet 048033 PUBLIC 1. Introduction This data sheet describes the functionality of the MFRC500 Integrated Circuit (IC). It includes the functional and electrical specifications and from a system and hardware viewpoint gives detailed information on how to design-in the device. Remark: The MFRC500 supports all variants of the MIFARE Classic, MIFARE 1K and MIFARE 4K RF identification protocols. To aid readability throughout this data sheet, the MIFARE Classic, MIFARE 1K and MIFARE 4K products and protocols have the generic name MIFARE. 2. General description The MFRC500 is a member of a new family of highly integrated reader ICs for contactless communication at 13.56 MHz. This family of reader ICs provide: outstanding modulation and demodulation for passive contactless communication a wide range of methods and protocols pin compatibility with the CLRC632, MFRC530, MFRC531 and SLRC400 All protocol layers of the ISO/IEC 14443 A are supported The receiver module provides a robust and efficient demodulation/decoding circuitry implementation for compatible transponder signals (see Section 9.10 on page 30). The digital module, manages the complete ISO/IEC 14443 A standard framing and error detection (parity and CRC). In addition, it supports the fast Crypto1 security algorithm for authenticating the MIFARE products (see Section 9.12 on page 35). The internal transmitter module (Section 9.9 on page 27) can directly drive an antenna designed for a proximity operating distance up to 100 mm without any additional active circuitry. A parallel interface can be directly connected to any 8-bit microprocessor to ensure reader/terminal design flexibility.MFRC500 NXP Semiconductors Highly Integrated ISO/IEC 14443 A Reader IC 3. Features and benefits 3.1 General Highly integrated analog circuitry for demodulating and decoding card response Buffered output drivers enable antenna connection using the minimum of external components Proximity operating distance up to 100 mm Supports the ISO/IEC 14443 A standard, parts 1 to 4 Supports MIFARE Classic protocol Crypto1 and secure non-volatile internal key memory Pin-compatible with the CLRC632, MFRC530, MFRC531 and the SLRC400 Parallel microprocessor interface with internal address latch and IRQ line Flexible interrupt handling Automatic detection of parallel microprocessor interface type 64-byte send and receive FIFO buffer Hard reset with low power function Software triggered Power-down mode Programmable timer Unique serial number User programmable start-up configuration Bit-oriented and byte oriented framing Independent power supply pins for analog, digital and transmitter modules Internal oscillator buffer optimized for low phase jitter enables 13.56 MHz quartz connection Clock frequency filtering 3.3 V operation for transmitter in short range and proximity applications 4. Applications Electronic payment systems Identification systems Access control systems Subscriber services Banking systems Digital content systems MFRC500 33 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3.3 15 March 2010 PUBLIC 048033 2 of 110