Document Number K61P256M150SF3 NXP Semiconductors Rev. 7, 02/2018 Data Sheet: Technical Data K61P256M150SF3 K61 Sub-Family Supports the following: MK61FX512VMJ15, MK61FN1M0VMJ15 Key features Security and integrity modules Hardware CRC module to support fast cyclic Operating Characteristics redundancy checks Voltage range: 1.71 to 3.6 V Tamper detect and secure storage Flash write voltage range: 1.71 to 3.6 V Hardware random-number generator Temperature range (ambient): -40 to 105C Hardware encryption supporting DES, 3DES, AES, Performance MD5, SHA-1, and SHA-256 algorithms Up to 150 MHz Arm Cortex-M4 core with DSP 128-bit unique identification (ID) number per chip instructions delivering 1.25 Dhrystone MIPS per Human-machine interface MHz Low-power hardware touch sensor interface (TSI) Memories and memory interfaces General-purpose input/output Up to 1024 KB program flash memory on non- Analog modules FlexMemory devices Four 16-bit SAR ADCs Up to 512 KB program flash memory on Programmable gain amplifier (PGA) (up to x64) FlexMemory devices integrated into each ADC Up to 512 KB FlexNVM on FlexMemory devices Two 12-bit DACs 16 KB FlexRAM on FlexMemory devices Four analog comparators (CMP) containing a 6-bit Up to 128 KB RAM DAC and programmable reference input Serial programming interface (EzPort) Voltage reference FlexBus external bus interface DDR controller interface Timers NAND flash controller interface Programmable delay block Two 8-channel motor control/general purpose/PWM Clocks timers 3 to 32 MHz crystal oscillator Two 2-channel quadrature decoder/general purpose 32 kHz crystal oscillator timers Multi-purpose clock generator IEEE 1588 timers System peripherals Periodic interrupt timers Multiple low-power modes to provide power 16-bit low-power timer optimization based on application requirements Carrier modulator transmitter Memory protection unit with multi-master Real-time clock protection 32-channel DMA controller, supporting up to 128 request sources External watchdog monitor Software watchdog Low-leakage wakeup unit NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Communication interfaces Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability USB high-/full-/low-speed On-the-Go controller with ULPI interface USB full-/low-speed On-the-Go controller with on-chip transceiver USB Device Charger detect (USBDCD) Two Controller Area Network (CAN) modules Three SPI modules Two I2C modules Six UART modules Secure Digital Host Controller (SDHC) Two I2S modules K61 Sub-Family, Rev. 7, 02/2018 2 NXP Semiconductors