MMPF0200F0ANES

NXP Semiconductors Document Number: MMPF0200 Rev. 7, 7/2019 Data Sheet: Technical Data 12 channel configurable power PF0200 management integrated circuit The PF0200 Power Management Integrated Circuit (PMIC) provides a highly programmable/ configurable architecture, with fully integrated power devices and minimal external components. With up to four buck converters, one boost POWER MANAGEMENT regulator, six linear regulators, RTC supply, and coin-cell charger, the PF0200 can provide power for a complete system, including applications processors, memory, and system peripherals, in a wide range of applications. With on-chip One Time Programmable (OTP) memory, the PF0200 is available in pre- programmed standard versions, or non-programmed to support custom programming. The PF0200 is especially suited to the i.MX 6SoloLite, i.MX 6Solo and i.MX 6DualLite versions of the i.MX 6 family of devices and is supported by full system level reference designs, and pre-programmed EP SUFFIX (E-TYPE) ES SUFFIX (WF-TYPE) versions of the device. This device is powered by SMARTMOS technology. 56 QFN 8X8 56 QFN 8X8 98ASA00405D 98ASA00589D Features: Applications Three to four buck converters, depending on configuration Tablets Boost regulator to 5.0 V output IPTV Six general purpose linear regulators Industrial Control Programmable output voltage, sequence, and timing Medical monitoring OTP (One Time Programmable) memory for device configuration Home automation/ alarm/ energy management Coin cell charger and RTC supply DDR termination reference voltage Power control logic with processor interface and event detection 2 I C control Individually programmable ON, OFF, and Standby modes PF0200 i.MX6X VREFDDR DDR MEMORY DDR Memory INTERFACE SW3A/B Processor Core SW1A/B Voltages External AMP Microphones SW2 Speakers SATA - FLASH SD-MMC/ SATA NAND - NOR NAND Mem. HDD Interfaces SWBST Audio Codec Parallel control/GPIOS Control Signals 2 2 I C Communication I C Communication Sensors VGEN1 Camera Camera GPS VGEN2 WAM MIPI GPS uPCIe MIPI VGEN3 VGEN4 HDMI LDVS Display VGEN5 USB Ethernet LICELL VGEN6 CAN Charger COINCELL Main Supply Front USB Rear Seat Rear USB Cluster/HUD POD Infotaiment POD Figure 1. Simplified application diagram NXP B.V. 2019.Table of Contents 1 Orderable parts . 3 2 Internal block diagram 4 3 Pin connections . 5 3.1 Pinout diagram 5 3.2 Pin definitions 6 4 General product characteristics . 9 4.1 Absolute maximum ratings 9 4.2 Thermal characteristics 10 4.3 Electrical characteristics . 11 5 General description . 14 5.1 Features 14 5.2 Functional block diagram . 15 5.3 Functional description . 15 6 Functional block requirements and behaviors . 17 6.1 Start-up 17 6.2 16 MHz and 32 kHz clocks . 22 6.3 Bias and references block description . 22 6.4 Power generation . 25 6.5 Control interface I2C block description 82 7 Typical applications . 99 7.1 Introduction . 99 7.2 PF0200 layout guidelines . 102 7.3 Thermal information 104 8 Packaging . 106 8.1 Packaging dimensions 106 9 Revision History . 113 PF0200 2 NXP Semiconductors