Document Number: MWIC930N Freescale Semiconductor Rev. 6, 5/2006 Technical Data RF LDMOS Wideband Integrated Power Amplifiers MWIC930NR1 The MWIC930N wideband integrated circuit is designed for CDMA and MWIC930GNR1 GSM/GSM EDGE applications. It uses Freescales newest High Voltage (26 to 28 Volts) LDMOS IC technology and integrates a multi-stage structure. Its wideband On-Chip integral matching circuitry makes it usable from 790 to 1000 MHz. The linearity performances cover all modulations for cellular applications: GSM, GSM EDGE, TDMA, N-CDMA and W-CDMA. 746-960 MHz, 30 W, 26-28 V Final Application SINGLE N-CDMA, GSM/GSM EDGE Typical Performance P1dB: V = 26 Volts, I = 90 mA, I = RF LDMOS WIDEBAND INTEGRATED DD DQ1 DQ2 240 mA, P = 30 Watts P1dB, Full Frequency Band (921-960 MHz) POWER AMPLIFIERS out Power Gain 30 dB Power Added Efficiency 45% Driver Application Typical Single-Carrier N-CDMA Performance: V = 27 Volts, I = DD DQ1 90 mA, I = 240 mA, P = 5 Watts Avg., Full Frequency Band DQ2 out (865-894 MHz), IS -95 (Pilot, Sync, Paging, Traffic Codes 8 Through 13), Channel Bandwidth = 1.2288 MHz. PAR = 9.8 dB 0.01% Probability on CCDF. CASE 1329-09 Power Gain 31 dB TO-272 WB-16 Power Added Efficiency 21% PLASTIC ACPR 750 kHz Offset -52 dBc in 30 kHz Bandwidth MWIC930NR1 Capable of Handling 5:1 VSWR, 26 Vdc, 921 MHz, 30 Watts CW Output Power Features Characterized with Series Equivalent Large-Signal Impedance Parameters On-Chip Matching (50 Ohm Input, DC Blocked, >4 Ohm Output) Integrated Quiescent Current Temperature Compensation with Enable/Disable Function CASE 1329A-03 (1) TO-272 WB-16 GULL On-Chip Current Mirror g Reference FET for Self Biasing Application m PLASTIC Integrated ESD Protection MWIC930GNR1 200C Capable Plastic Package N Suffix Indicates Lead-Free Terminations. RoHS Compliant. In Tape and Reel. R1 Suffix = 500 Units per 44 mm, 13 inch Reel. V RD2 GND 1 GND 16 V V RG2 RD2 2 15 NC V 3 RG2 V DS1 4 V DS1 V 5 RD1 RF out/ RF 6 14 in V DS2 RF V /RF in DS2 out V RG1 7 V GS1 8 V RD1 V GS2 9 NC 10 13 NC V RG1 GND GND 11 12 (Top View) V GS1 Quiescent Current Temperature Compensation Note: Exposed backside flag is source V GS2 terminal for transistors. Figure 1. Functional Block Diagram Figure 2. Pin Connections 1. Refer to AN1987/D, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to Table 1. Maximum Ratings Rating Symbol Value Unit Drain-Source Voltage V -0.5, +65 Vdc DSS Gate-Source Voltage V -0.5, +15 Vdc GS Storage Temperature Range T -65 to +175 C stg Operating Junction Temperature T 200 C J Table 2. Thermal Characteristics (1,2) Characteristic Symbol Value Unit Thermal Resistance, Junction to Case R C/W JC GSM Application Stage 1, 26 Vdc, I = 90 mA 5.9 DQ (P = 30 W CW) Stage 2, 26 Vdc, I = 240 mA 1.4 out DQ GSM EDGE Application Stage 1, 27 Vdc, I = 90 mA 6.5 DQ (P = 15 W CW) Stage 2, 27 Vdc, I = 240 mA 1.7 out DQ CDMA Application Stage 1, 27 Vdc, I = 90 mA 6.5 DQ (P = 5 W CW) Stage 2, 27 Vdc, I = 240 mA 1.8 out DQ Table 3. ESD Protection Characteristics Test Conditions Class Human Body Model 1 (Minimum) Machine Model M3 (Minimum) Charge Device Model C2 (Minimum) Table 4. Moisture Sensitivity Level Test Methodology Rating Package Peak Temperature Unit Per JESD 22-A113, IPC/JEDEC J-STD-020 3 260 C Table 5. Electrical Characteristics (T = 25C, unless otherwise noted) C Characteristic Symbol Min Typ Max Unit Functional Tests (In Freescale Test Fixture, 50 ohm system) V = 27 Vdc, I = 90 mA, I = 240 mA, P = 5 W Avg. N-CDMA, DD DQ1 DQ2 out f = 880 MHz, Single-Carrier N-CDMA, 1.2288 MHz Channel Bandwidth Carrier. ACPR measured in 30 kHz Bandwidth 750 MHz Offset. PAR = 9.8 dB 0.01% Probability on CCDF Power Gain G 28 31 dB ps Power Added Efficiency PAE 18 21 % Input Return Loss IRL -12 -9 dB (f = 880 MHz) Adjacent Channel Power Ratio ACPR -52 -48 dBc Typical Performances (In Freescale Test Fixture) V = 26 Vdc, I = 90 mA, I = 240 mA, 840 MHz<Frequency<920 MHz DD DQ1 DQ2 (2) Quiescent Current Accuracy over Temperature % Stage 1 with 33.2 k Gate Feed Resistors (-30 to 115C) I 2.5 1QT Stage 2 with 47.5 k Gate Feed Resistors (-30 to 115C) I 2.5 2QT Gain Flatness in 80 MHz Bandwidth P = 5 W CW G 0.3 dB out F Deviation from Linear Phase in 80 MHz Bandwidth P = 5 W CW 0.6 out Delay P = 5 W CW Including Output Matching Delay 3 ns out Part-to-Part Phase Variation P = 5 W CW 15 out 1. Refer to AN1955/D, Thermal Measurement Methodology of RF Power Amplifiers. Go to