N74F164D,602 NXP

INTEGRATED CIRCUITS 74F164 8-bit serial-in parallel-out shift register Product specification 2000 Dec 18 Supersedes data of 1995 Sep 22 Philips Semiconductors Product specification 8-bit serial-in parallel-out shift register 74F164 FEATURES PIN CONFIGURATION Gated serial data inputs Dsa 1 14 V CC Typical shift frequency of 100MHz Dsb 2 13 Q7 Asynchronous Master Reset Q0 3 12 Q6 Buffered clock and data inputs Q1 4 11 Q5 Fully synchronous data transfer Q2 5 10 Q4 Industrial temperature range available (40 to +85 C) Q3 6 9 MR GND 7 8 CP DESCRIPTION The 74F164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered SF00717 through one of two inputs (Dsa, Dsb) either input can be used as an active High enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied High. TYPICAL SUPPLY TYPE TYPICAL f max CURRENT (TOTAL) Data shifts one place to the right on each Low-to-High transition of the clock (CP) input, and enters into Q0 the logical AND of the two 74F164 100MHz 33 mA data inputs (Dsa, Dsb) that existed one setup time before the rising edge. A Low level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs Low. ORDERING INFORMATION ORDER CODE DRADRAWINGWING DESCRIPTION COMMERCIAL RANGE INDUSTRIAL RANGE NUMBER V = 5 V 10%, T = 0 to +70 C V = 5 V 10%, T = 40 to +85 C CC amb CC amb 14-pin plastic DIP 74F164N I74F164N SOT27-1 14-pin plastic SO 74F164D I74F164D SOT108-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE 74F (U.L.) LOAD VALUE PINS DESCRIPTION HIGH / LOW HIGH / LOW Dsa, Dsb Data inputs 1.0 / 1.0 20 A / 0.6 mA CP Clock pulse input (active rising edge) 1.0 / 1.0 20 A / 0.6 mA MR Master reset input (active-Low) 1.0 / 1.0 20 A / 0.6 mA Q0 Q7 Data outputs 50 / 33 1.0 mA / 20 mA One (1.0) FAST unit load is defined as: 20 A in the High state and 0.6 mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL SRG8 8 C1/ 9 R 12 1 & 3 1D 2 Dsa Dsb 8 CP 4 MR 9 5 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 6 10 3 4 5 6 10 11 12 13 11 12 13 V = Pin 14 CC GND = Pin 7 SF00714 SF00713 2 2000 Dec 18 853-0348 25264